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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: Richard Henderson <rth@twiddle.net>,
	David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	bharata@linux.vnet.ibm.com,
	Avinesh Kumar <avinesku@linux.vnet.ibm.com>
Subject: Re: [Qemu-devel] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions
Date: Thu, 24 Nov 2016 13:52:53 +0530	[thread overview]
Message-ID: <87wpftwale.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> (raw)
In-Reply-To: <0331c36b-f131-5aa5-d963-410c3ff96716@twiddle.net>

Richard Henderson <rth@twiddle.net> writes:

> On 11/24/2016 06:53 AM, Nikunj A Dadhania wrote:
>> David Gibson <david@gibson.dropbear.id.au> writes:
>>
>>> [ Unknown signature status ]
>>> On Wed, Nov 23, 2016 at 05:07:18PM +0530, Nikunj A Dadhania wrote:
>>>> From: Avinesh Kumar <avinesku@linux.vnet.ibm.com>
>>>>
>>>> vextublx:  Vector Extract Unsigned Byte Left
>>>> vextuhlx:  Vector Extract Unsigned Halfword Left
>>>> vextuwlx:  Vector Extract Unsigned Word Left
>>>>
>>>> Signed-off-by: Avinesh Kumar <avinesku@linux.vnet.ibm.com>
>>>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>>>
>>> So, when I suggested doing these without helpers before, I had
>>> forgotten that the non-byte versions can straddle the word boundary.
>>> Given that the offset is in a register, not the instruction that does
>>> make it complicated.
>>>
>>> But, this version also relies on working 128-bit arithmetic, AFAICT
>>> this will just fail to build if CONFIG_INT128 isn't defined.
>>
>> It has both the implementation, just that the defines might have
>> confused you:
>>
>> #if defined(HOST_WORDS_BIGENDIAN)
>>
>> #  if defined(CONFIG_INT128)
>> #  else
>> #  endif
>>
>> #else /* !defined (HOST_WORDS_BIGENDIAN) */
>>
>> #  if defined(CONFIG_INT128)
>> #  else
>> #  endif
>>
>> #endif
>
> In include/qemu/int128.h, we do have int128_rshift.  So you don't *really* have 
> to do this by hand, exactly.

Sure, let me add int128_extract as well. Will be helpful.

Regards
Nikunj

  reply	other threads:[~2016-11-24  8:23 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-23 11:37 [Qemu-devel] [PATCH v1 ppc-for-2.9 00/10] POWER9 TCG enablements - part8 Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 01/10] target-ppc: Consolidate instruction decode helpers Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 02/10] target-ppc: rename CRF_* defines as CRF_*_BIT Nikunj A Dadhania
2016-11-24  0:23   ` David Gibson
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 03/10] target-ppc: Fix xscmpodp and xscmpudp instructions Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 04/10] target-ppc: Add xscmpexp[dp, qp] instructions Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 05/10] target-ppc: Add xscmpoqp and xscmpuqp instructions Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 06/10] target-ppc: implement lxsd and lxssp instructions Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 07/10] target-ppc: implement stxsd and stxssp Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 08/10] target-ppc: implement lxv/lxvx and stxv/stxvx Nikunj A Dadhania
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions Nikunj A Dadhania
2016-11-24  1:02   ` David Gibson
2016-11-24  5:53     ` Nikunj A Dadhania
2016-11-24  8:14       ` Richard Henderson
2016-11-24  8:22         ` Nikunj A Dadhania [this message]
2016-11-23 11:37 ` [Qemu-devel] [PATCH v1 10/10] target-ppc: add vextu[bhw]rx instructions Nikunj A Dadhania
2016-11-24  0:56 ` [Qemu-devel] [PATCH v1 ppc-for-2.9 00/10] POWER9 TCG enablements - part8 David Gibson

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