From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43386) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zi1Us-0003OM-4y for qemu-devel@nongnu.org; Fri, 02 Oct 2015 10:39:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zi1Um-00037q-16 for qemu-devel@nongnu.org; Fri, 02 Oct 2015 10:39:42 -0400 Received: from mail-wi0-f181.google.com ([209.85.212.181]:36336) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zi1Ul-00037m-R4 for qemu-devel@nongnu.org; Fri, 02 Oct 2015 10:39:35 -0400 Received: by wicgb1 with SMTP id gb1so36000664wic.1 for ; Fri, 02 Oct 2015 07:39:35 -0700 (PDT) References: <1443436639-6603-1-git-send-email-serge.fdrv@gmail.com> <874midu5mw.fsf@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: Date: Fri, 02 Oct 2015 15:39:32 +0100 Message-ID: <87wpv5s5az.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH] target-arm: Add MDCR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Sergey Fedorov , QEMU Developers Peter Maydell writes: > On 29 September 2015 at 07:00, Alex Bennée wrote: >> >> Sergey Fedorov writes: >> >>> Signed-off-by: Sergey Fedorov >>> --- >>> >>> This patch is a prerequisite for a debug exception routing patch: >>> https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg03542.html >>> >>> target-arm/cpu-qom.h | 1 + >>> target-arm/cpu.c | 1 + >>> target-arm/cpu.h | 1 + >>> target-arm/cpu64.c | 1 + >>> target-arm/helper.c | 13 +++++++++++++ >>> 5 files changed, 17 insertions(+) >>> >>> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h >>> index 25fb1ce..d2b0769 100644 >>> --- a/target-arm/cpu-qom.h >>> +++ b/target-arm/cpu-qom.h >>> @@ -167,6 +167,7 @@ typedef struct ARMCPU { >>> uint64_t id_aa64mmfr0; >>> uint64_t id_aa64mmfr1; >>> uint32_t dbgdidr; >>> + uint32_t mdcr; >>> uint32_t clidr; >>> uint64_t mp_affinity; /* MP ID without feature bits */ >>> /* The elements of this array are the CCSIDR values for each cache, >>> diff --git a/target-arm/cpu.c b/target-arm/cpu.c >>> index d7b4445..6474c0d 100644 >>> --- a/target-arm/cpu.c >>> +++ b/target-arm/cpu.c >>> @@ -1125,6 +1125,7 @@ static void cortex_a15_initfn(Object *obj) >>> cpu->id_isar3 = 0x11112131; >>> cpu->id_isar4 = 0x10011142; >>> cpu->dbgdidr = 0x3515f021; >>> + cpu->mdcr = 0x00000006; >>> cpu->clidr = 0x0a200023; >>> cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ >>> cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ >>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >>> index 1b80516..d57ed20 100644 >>> --- a/target-arm/cpu.h >>> +++ b/target-arm/cpu.h >>> @@ -380,6 +380,7 @@ typedef struct CPUARMState { >>> uint64_t dbgwvr[16]; /* watchpoint value registers */ >>> uint64_t dbgwcr[16]; /* watchpoint control registers */ >>> uint64_t mdscr_el1; >>> + uint64_t mdcr_el2; >> >> Given we already have banked el3 regs shouldn't this be: >> >> uint64_6 mdcr_el[4] >> >> ? > > You could argue either way, but since there's only an > MDCR_EL2 and an MDCR_EL3 and they're not really the same > field format there won't be any code that wants to do > mdcr_el[x], so I think calling the field mdcr_el2 is ok. Fair enough that makes sense. -- Alex Bennée