From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35649) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCvXI-0002lo-1N for qemu-devel@nongnu.org; Tue, 05 Mar 2013 12:20:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCvXE-0005Ly-4e for qemu-devel@nongnu.org; Tue, 05 Mar 2013 12:20:19 -0500 Received: from e23smtp01.au.ibm.com ([202.81.31.143]:43658) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCvXD-0005La-KB for qemu-devel@nongnu.org; Tue, 05 Mar 2013 12:20:16 -0500 Received: from /spool/local by e23smtp01.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 6 Mar 2013 03:14:10 +1000 Received: from d23relay03.au.ibm.com (d23relay03.au.ibm.com [9.190.235.21]) by d23dlp01.au.ibm.com (Postfix) with ESMTP id C335E2CE804C for ; Wed, 6 Mar 2013 04:20:06 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay03.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r25HK3Z749742006 for ; Wed, 6 Mar 2013 04:20:03 +1100 Received: from d23av03.au.ibm.com (loopback [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r25HK6Rk020375 for ; Wed, 6 Mar 2013 04:20:06 +1100 From: Anthony Liguori In-Reply-To: <1362495898-15352-3-git-send-email-pbonzini@redhat.com> References: <1362495898-15352-1-git-send-email-pbonzini@redhat.com> <1362495898-15352-3-git-send-email-pbonzini@redhat.com> Date: Tue, 05 Mar 2013 11:20:02 -0600 Message-ID: <87wqtlrcfx.fsf@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Re: [Qemu-devel] [PATCH 2/3] pc: port 92 reset requires a low->high transition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: dwmw2@infradead.org, lersek@redhat.com Paolo Bonzini writes: > The PIIX datasheet says that "before another INIT pulse can be > generated via [port 92h], [bit 0] must be written back to a > zero. > > This bug is masked right now because a full reset will clear the > value of port 92h. But once we implement soft reset correctly, > the next attempt to enable the A20 line by setting bit 1 (and > leaving the others untouched) will cause another reset. > > Signed-off-by: Paolo Bonzini Reviewed-by: Anthony Liguori Regards, Anthony Liguori > --- > hw/pc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/pc.c b/hw/pc.c > index 07caba7..523db1f 100644 > --- a/hw/pc.c > +++ b/hw/pc.c > @@ -435,11 +435,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, > unsigned size) > { > Port92State *s = opaque; > + int oldval = s->outport; > > DPRINTF("port92: write 0x%02x\n", val); > s->outport = val; > qemu_set_irq(*s->a20_out, (val >> 1) & 1); > - if (val & 1) { > + if ((val & 1) && !(oldval & 1)) { > qemu_system_reset_request(); > } > } > -- > 1.8.1.4