From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:36519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SxIlj-0001jU-NO for qemu-devel@nongnu.org; Fri, 03 Aug 2012 10:22:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SxIlf-0004DT-Jy for qemu-devel@nongnu.org; Fri, 03 Aug 2012 10:22:23 -0400 Received: from mail-gg0-f173.google.com ([209.85.161.173]:49783) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SxIlf-0004DN-FX for qemu-devel@nongnu.org; Fri, 03 Aug 2012 10:22:19 -0400 Received: by ggnp1 with SMTP id p1so868016ggn.4 for ; Fri, 03 Aug 2012 07:22:19 -0700 (PDT) From: Anthony Liguori In-Reply-To: References: <1343873409-8571-1-git-send-email-david@gibson.dropbear.id.au> <1343873409-8571-3-git-send-email-david@gibson.dropbear.id.au> <501AA071.3030406@suse.de> <87vch1i1va.fsf@codemonkey.ws> <501AC915.5080004@suse.de> <87lihx84m4.fsf@codemonkey.ws> <20120803023726.GH12733@truffala.fritz.box> <878vdwm6dt.fsf@codemonkey.ws> Date: Fri, 03 Aug 2012 09:22:15 -0500 Message-ID: <87wr1gnjhk.fsf@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Re: [Qemu-devel] [PATCH 2/2] pseries: Use new hook to correct reset sequence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Igor Mammedov , agraf@suse.de, qemu-devel@nongnu.org, Andreas =?utf-8?Q?F=C3=A4r?= =?utf-8?Q?ber?= , David Gibson Peter Maydell writes: > On 3 August 2012 14:50, Anthony Liguori wrote: >> There ought to be a hierarchy (based on composition) that reset flows >> through. > > I think saying "the reset tree is isomorphic to the composition tree" > is making the same mistake that qbus did with "the bus tree is > isomorphic to the composition tree". The stakes are lower for reset > and we can probably get away with it, but it really isn't how the > hardware works... It flows through the composition tree by default, but can be overridden at any point. For instance, the i440fx will absolutely want to override this behavior such that it can flow reset through the PCI bus (which is how the PIIX3 would be reset). However, the PIIX3 has no need to override this behavior. So this model should work very well for most types of virtual hardware. But it doesn't provide for a mechanism to "after all devices are initialized, build FDT in guest memory, then set the CPU registers to point to it". There's no logical device that has a scope like that that also has the mechanism to get that type of hook in the reset path. That's why we need to have the QEMUMachine::reset() hook. Regards, Anthony Liguori > > -- PMM