From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1ITPXw-00042O-W3 for qemu-devel@nongnu.org; Thu, 06 Sep 2007 18:09:57 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1ITPXv-00040P-T1 for qemu-devel@nongnu.org; Thu, 06 Sep 2007 18:09:56 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1ITPXv-000401-NW for qemu-devel@nongnu.org; Thu, 06 Sep 2007 18:09:55 -0400 Received: from mnemosyne.csbnet.se ([193.11.254.193]) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1ITPXu-0004ll-TC for qemu-devel@nongnu.org; Thu, 06 Sep 2007 18:09:55 -0400 Received: from industria.csbnet.se ([193.11.254.200] ident=Debian-exim) by mnemosyne.csbnet.se with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1ITPXr-0006SM-UY for qemu-devel@nongnu.org; Fri, 07 Sep 2007 00:09:51 +0200 From: goran@weinholt.se (=?utf-8?Q?G=C3=B6ran?= Weinholt) Date: Fri, 07 Sep 2007 00:10:59 +0200 Message-ID: <87wsv3xx58.fsf@industria.csbnet.se> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH] amd64 support in cpu_gdb_read_registers() Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi, earlier this week I needed to use gdb with QEMU to debug some software of mine that runs in a 64-bit code segment. But gdb only gave me nonsense data because QEMU sent it a normal i386 register dump. The following patch fixes cpu_gdb_read_registers() so that it works for 64-bit code segments. It's based on the 32-bit version and I haven't verified if the byte swapping and floating point stuff is correct. cpu_gdb_write_registers() also needs to be fixed, but I don't have any personal need for it right now and I also don't understand why it loads the segment registers only when CONFIG_USER_ONLY is defined. Seems to me like it should be the other way around, so I don't dare suggest a patch. Index: gdbstub.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RCS file: /sources/qemu/qemu/gdbstub.c,v retrieving revision 1.63 diff -u -r1.63 gdbstub.c --- gdbstub.c 6 Sep 2007 00:18:13 -0000 1.63 +++ gdbstub.c 6 Sep 2007 17:22:51 -0000 @@ -225,8 +225,54 @@ =20 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) { - uint32_t *registers =3D (uint32_t *)mem_buf; int i, fpus; +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + /* This corresponds with amd64_register_info[] in gdb/amd64-tdep.c= */ + uint64_t *registers =3D (uint64_t *)mem_buf; + + registers[0] =3D tswap64(env->regs[R_EAX]); + registers[1] =3D tswap64(env->regs[R_EBX]); + registers[2] =3D tswap64(env->regs[R_ECX]); + registers[3] =3D tswap64(env->regs[R_EDX]); + registers[4] =3D tswap64(env->regs[R_ESI]); + registers[5] =3D tswap64(env->regs[R_EDI]); + registers[6] =3D tswap64(env->regs[R_EBP]); + registers[7] =3D tswap64(env->regs[R_ESP]); + for(i =3D 8; i < 16; i++) { + registers[i] =3D tswap64(env->regs[i]); + } + registers[16] =3D tswap64(env->eip); + uint32_t *registers32 =3D (uint32_t*) ®isters[17]; + registers32[0] =3D tswap32(env->eflags); + registers32[1] =3D tswap32(env->segs[R_CS].selector); + registers32[2] =3D tswap32(env->segs[R_SS].selector); + registers32[3] =3D tswap32(env->segs[R_DS].selector); + registers32[4] =3D tswap32(env->segs[R_ES].selector); + registers32[5] =3D tswap32(env->segs[R_FS].selector); + registers32[6] =3D tswap32(env->segs[R_GS].selector); + /* XXX: convert floats */ + for(i =3D 0; i < 8; i++) { + memcpy(mem_buf + 16 * 8 + 7 * 4 + i * 10, &env->fpregs[i], 10); + } + registers32[27] =3D tswap32(env->fpuc); /* fctrl */ + fpus =3D (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; + registers32[28] =3D tswap32(fpus); /* fstat */ + registers32[29] =3D 0; /* ftag */ + registers32[30] =3D 0; /* fiseg */ + registers32[31] =3D 0; /* fioff */ + registers32[32] =3D 0; /* foseg */ + registers32[33] =3D 0; /* fooff */ + registers32[34] =3D 0; /* fop */ + for(i =3D 0; i < 16; i++) { + memcpy(mem_buf + 16 * 8 + 35 * 4 + i * 16, &env->xmm_regs[i], = 16); + } + registers32[99] =3D tswap32(env->mxcsr); + + return 8 * 17 + 4 * 7 + 10 * 8 + 4 * 8 + 16 * 16 + 4; + } +#endif + uint32_t *registers =3D (uint32_t *)mem_buf; =20 for(i =3D 0; i < 8; i++) { registers[i] =3D env->regs[i]; --=20 G=C3=B6ran Weinholt I was making donuts and now I'm on a bus!