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Wed, 26 Nov 2025 02:31:49 -0800 (PST) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47906cb9715sm37672155e9.2.2025.11.26.02.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Nov 2025 02:31:49 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 42E305F7DD; Wed, 26 Nov 2025 10:31:48 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Jim MacArthur Cc: qemu-devel@nongnu.org Subject: Re: [PATCH 3/3] tests: Add test for ASID2 and write/read of feature bits In-Reply-To: (Jim MacArthur's message of "Tue, 25 Nov 2025 21:29:58 +0000") References: <20251120125833.123813-1-jim.macarthur@linaro.org> <20251120125833.123813-4-jim.macarthur@linaro.org> <87fra38ogg.fsf@draig.linaro.org> User-Agent: mu4e 1.12.14-pre3; emacs 30.1 Date: Wed, 26 Nov 2025 10:31:48 +0000 Message-ID: <87y0nt5bl7.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Jim MacArthur writes: > On Mon, 24 Nov 2025 at 15:01, Alex Benn=C3=A9e w= rote: >> If we instead use this to test for the presence of the feature and then.= .. >> >> > + >> > + asm("msr " TCR2_EL1 ", %[x0]\n\t" >> > + "mrs %[x1], " TCR2_EL1 "\n\t" >> > + : [x1] "=3Dr" (out) >> > + : [x0] "r" (in)); >> > + >> > + if ((out & feature_mask) =3D=3D in) { >> > + ml_printf("OK\n"); >> > + return 0; >> > + } else { >> > + ml_printf("FAIL: read value %lx !=3D written value %lx\n", >> > + out & feature_mask, in); >> > + return 1; >> > + } >> >> extend this part to check the bits are behaving as the feature dictates >> then we can add a second test like this (Makefile.softmmu-target): >> >> run-asid2-oldcpu: asid2 >> $(call run-test, $<, \ >> $(QEMU) -monitor none -display none \ >> -chardev file$(COMMA)path=3D$<.out$(COMMA)id=3Doutpu= t \ >> $(QEMU_OPTS) $<) >> >> run-asid2-oldcpu: QEMU_OPTS=3D-M virt -cpu cortex-a72 -display none $(= QEMU_BASE_ARGS) -kernel >> >> EXTRA_RUNS +=3D run-asid2-oldcpu >> >> Although its a bit clunky - one day I'll get around to converting this >> lot to meson. > > Good idea, but as far as I can see cortex-a72 doesn't implement > FEAT_TCR2, and nor does anything other than cpu-max, so the write and > read to TCR2_EL1 will be undefined behaviour (and causes an error in > the test). I could (and probably should) add a test for FEAT_TCR2 as > well, but it won't test anything more than my original test covers. Ahh I see - until we have a new CPU type that has FEAT_TCR2 without ASID2 there isn't much point jumping the hoops to test the edge case. I think the most modern non-max CPU we have at the moment is the neoverse-n2. We have TRMs for the -n3 and -v3's now so we could check those to see if we have enough of the features to add them to the list and if they meet the criteria of FEAT_TCR2 without FEAT_ASID2. In the meantime no need to hold this up: Reviewed-by: Alex Benn=C3=A9e > > Jim --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro