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Wed, 25 Jun 2025 16:38:02 +0000 (UTC) Received: from localhost (mschlens-int.str.redhat.com [10.33.192.203]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id AD52F1956096; Wed, 25 Jun 2025 16:37:59 +0000 (UTC) From: Cornelia Huck To: Peter Maydell , eric.auger@redhat.com Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, kvmarm@lists.linux.dev, richard.henderson@linaro.org, alex.bennee@linaro.org, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, shameerali.kolothum.thodi@huawei.com, armbru@redhat.com, berrange@redhat.com, abologna@redhat.com, jdenemar@redhat.com, agraf@csgraf.de, shahuang@redhat.com, mark.rutland@arm.com, philmd@linaro.org, pbonzini@redhat.com Subject: Re: [PATCH v8 00/14] arm: rework id register storage In-Reply-To: Organization: "Red Hat GmbH, Sitz: Werner-von-Siemens-Ring 12, D-85630 Grasbrunn, Handelsregister: Amtsgericht =?utf-8?Q?M=C3=BCnchen=2C?= HRB 153243, =?utf-8?Q?Gesch=C3=A4ftsf=C3=BChrer=3A?= Ryan Barnhart, Charles Cachera, Avril Crosse O'Flaherty" References: <20250617153931.1330449-1-cohuck@redhat.com> <05e903b3-02bf-4c04-ac2b-cdec0b45fe3f@redhat.com> User-Agent: Notmuch/0.38.3 (https://notmuchmail.org) Date: Wed, 25 Jun 2025 18:37:57 +0200 Message-ID: <87y0tfhj4q.fsf@redhat.com> MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jun 25 2025, Peter Maydell wrote: > On Wed, 25 Jun 2025 at 10:10, Eric Auger wrote: >> However there are other checkpatch errors besides the one you reported, in >> 52873a54ad arm/cpu: Store aa64isar0/aa64zfr0 into the idregs arrays >> ERROR: line over 90 characters >> #388: FILE: target/arm/kvm.c:225: >> + return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> >> CP_REG_ARM64_SYSREG_OP0_SHIFT, >> >> ERROR: line over 90 characters >> #389: FILE: target/arm/kvm.c:226: >> + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> >> CP_REG_ARM64_SYSREG_OP1_SHIFT, >> >> ERROR: line over 90 characters >> #390: FILE: target/arm/kvm.c:227: >> + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> >> CP_REG_ARM64_SYSREG_CRN_SHIFT, >> >> ERROR: line over 90 characters >> #391: FILE: target/arm/kvm.c:228: >> + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> >> CP_REG_ARM64_SYSREG_CRM_SHIFT, >> >> ERROR: line over 90 characters >> #392: FILE: target/arm/kvm.c:229: >> + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> >> CP_REG_ARM64_SYSREG_OP2_SHIFT); >> >> WARNING: line over 80 characters >> #396: FILE: target/arm/kvm.c:233: >> +static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf, >> ARMIDRegisterIdx index) > > The last one of those is probably easily fixed, but note the general > remark in style.rst that it's better to have an overlong line than > one with an awkward and unreadable wrapping. (We ought to fix > checkpatch and style.rst to agree on whether to warn or error and > whether that should be at 90 chars or 100 chars, but that would require > reopening an old style argument and it's too much effort.) I would not disagree with fixing the last one if wanted, but I think the others are more readable if we do not try to break them up. > >> 5f15ebdf3f arm/cpu: Add sysreg definitions in cpu-sysregs.h >> ERROR: Macros with complex values should be enclosed in parenthesis >> #56: FILE: target/arm/cpu-sysregs.h:21: >> +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) NAME##_IDX, >> >> ERROR: Macros with complex values should be enclosed in parenthesis >> #64: FILE: target/arm/cpu-sysregs.h:29: >> +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ >> + SYS_##NAME = ENCODE_ID_REG(OP0, OP1, CRN, CRM, OP2), >> >> ERROR: Macros with complex values should be enclosed in parenthesis >> #203: FILE: target/arm/cpu64.c:40: >> +#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) \ >> + [NAME##_IDX] = SYS_##NAME, > > This is checkpatch not being able to cope with more complex > uses of the preprocessor; the warning only makes sense for > "acts like a function" macros. Yep, that's why I ignored it. In general, should we mention that we intentionally ignored checkpatch.pl feedback, or would that be just noise?