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Thu, 05 Sep 2024 08:26:30 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id BEA405F8BA; Thu, 5 Sep 2024 16:26:29 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Rowan Hart Cc: qemu-devel@nongnu.org, Alexandre Iooss , Pierrick Bouvier , Mahmoud Mandour Subject: Re: [PATCH 0/1] plugins: add API to read guest CPU memory from hwaddr In-Reply-To: <20240828063224.291503-1-rowanbhart@gmail.com> (Rowan Hart's message of "Tue, 27 Aug 2024 23:32:23 -0700") References: <20240828063224.291503-1-rowanbhart@gmail.com> User-Agent: mu4e 1.12.6; emacs 29.4 Date: Thu, 05 Sep 2024 16:26:29 +0100 Message-ID: <87y146ruje.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rowan Hart writes: > This patch adds a single API function which allows reading from a guest > CPU physical address. > > I don't know of a good way to add a self-contained test for this feature > to tests/tcg/plugins, but I did come up with a small test case to > demonstrate the functionality using peiyuanix/riscv-os: We have bare metal system tests (hello and memory) for i386, alpha, loongarch64, aarch64 and arm. If you fancy having a go at implementing a boot.S for riscv64 that would be super helpful for the check-tcg tests as a whole. See: tests/tcg/i386/system/boot.S tests/tcg/alpha/system/boot.S tests/tcg/loongarch64/system/boot.S tests/tcg/aarch64/system/boot.S tests/tcg/x86_64/system/boot.S tests/tcg/arm/system/boot.S for what is needed (basically a MMU-enabled flat memory map and some sort of emit char helper, probably using semihosting in this case) > > First, grab and build the firmware code: > > curl -o firmware.S https://raw.githubusercontent.com/peiyuanix/riscv-os/m= ain/03-Bare-Metal-Hello-RISC-V/firmware.s > curl -o firmware.x https://raw.githubusercontent.com/peiyuanix/riscv-os/m= ain/03-Bare-Metal-Hello-RISC-V/firmware.ld > riscv64-linux-gnu-as firmware.S -o firmware.o > riscv64-linux-gnu-ld -T firmware.x -o firmare firmware.o > riscv64-linux-gnu-objcopy -O binary -S firmware firmware.bin > > Next, grab and build the plugin (just dumps from phys address on first > instruction executed): > > curl -o dump-riscv-firmware.c https://gist.githubusercontent.com/novafaci= ng/5abc08052fab671a0fb26547810b4c55/raw/33772d614d6e36eae30e3405af34f149d7c= c608b/dump-riscv-firmware.c > gcc -rdynamic -shared -fPIC -Iinclude/qemu $(pkg-config --cflags --libs g= lib-2.0) -o libdump-riscv-firmware.so dump-riscv-firmware.c > --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro