From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH v2 15/22] tcg: Remove TCG_TARGET_HAS_direct_jump
Date: Tue, 17 Jan 2023 18:25:47 +0000 [thread overview]
Message-ID: <87y1q110hv.fsf@linaro.org> (raw)
In-Reply-To: <20230109014248.2894281-16-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> We now have the option to generate direct or indirect
> goto_tb depending on the dynamic displacement, thus
> the define is no longer necessary or completely accurate.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target.h | 1 -
> tcg/arm/tcg-target.h | 1 -
> tcg/i386/tcg-target.h | 1 -
> tcg/loongarch64/tcg-target.h | 1 -
> tcg/mips/tcg-target.h | 1 -
> tcg/ppc/tcg-target.h | 1 -
> tcg/riscv/tcg-target.h | 1 -
> tcg/s390x/tcg-target.h | 1 -
> tcg/sparc64/tcg-target.h | 1 -
> tcg/tci/tcg-target.h | 1 -
> accel/tcg/cpu-exec.c | 13 ++++++-------
> tcg/tcg.c | 1 -
> tcg/arm/tcg-target.c.inc | 1 -
> tcg/mips/tcg-target.c.inc | 1 -
> tcg/riscv/tcg-target.c.inc | 1 -
> tcg/s390x/tcg-target.c.inc | 3 +++
> tcg/tci/tcg-target.c.inc | 1 -
> 17 files changed, 9 insertions(+), 22 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index a585d035d9..6067446b03 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -123,7 +123,6 @@ typedef enum {
> #define TCG_TARGET_HAS_muls2_i64 0
> #define TCG_TARGET_HAS_muluh_i64 1
> #define TCG_TARGET_HAS_mulsh_i64 1
> -#define TCG_TARGET_HAS_direct_jump 1
>
> #define TCG_TARGET_HAS_v64 1
> #define TCG_TARGET_HAS_v128 1
> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
> index d347a5dc53..91b8954804 100644
> --- a/tcg/arm/tcg-target.h
> +++ b/tcg/arm/tcg-target.h
> @@ -121,7 +121,6 @@ extern bool use_neon_instructions;
> #define TCG_TARGET_HAS_mulsh_i32 0
> #define TCG_TARGET_HAS_div_i32 use_idiv_instructions
> #define TCG_TARGET_HAS_rem_i32 0
> -#define TCG_TARGET_HAS_direct_jump 0
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #define TCG_TARGET_HAS_v64 use_neon_instructions
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index d3705da2ed..5797a55ea0 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -141,7 +141,6 @@ extern bool have_movbe;
> #define TCG_TARGET_HAS_muls2_i32 1
> #define TCG_TARGET_HAS_muluh_i32 0
> #define TCG_TARGET_HAS_mulsh_i32 0
> -#define TCG_TARGET_HAS_direct_jump 1
>
> #if TCG_TARGET_REG_BITS == 64
> /* Keep target addresses zero-extended in a register. */
> diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h
> index 5782c6887c..1c3e48d662 100644
> --- a/tcg/loongarch64/tcg-target.h
> +++ b/tcg/loongarch64/tcg-target.h
> @@ -128,7 +128,6 @@ typedef enum {
> #define TCG_TARGET_HAS_clz_i32 1
> #define TCG_TARGET_HAS_ctz_i32 1
> #define TCG_TARGET_HAS_ctpop_i32 0
> -#define TCG_TARGET_HAS_direct_jump 1
> #define TCG_TARGET_HAS_brcond2 0
> #define TCG_TARGET_HAS_setcond2 0
> #define TCG_TARGET_HAS_qemu_st8_i32 0
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index 82b40100cf..7bc8e15293 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -134,7 +134,6 @@ extern bool use_mips32r2_instructions;
> #define TCG_TARGET_HAS_muluh_i32 1
> #define TCG_TARGET_HAS_mulsh_i32 1
> #define TCG_TARGET_HAS_bswap32_i32 1
> -#define TCG_TARGET_HAS_direct_jump 0
>
> #if TCG_TARGET_REG_BITS == 64
> #define TCG_TARGET_HAS_add2_i32 0
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index 5ffb41fb57..f253184915 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -108,7 +108,6 @@ extern bool have_vsx;
> #define TCG_TARGET_HAS_muls2_i32 0
> #define TCG_TARGET_HAS_muluh_i32 1
> #define TCG_TARGET_HAS_mulsh_i32 1
> -#define TCG_TARGET_HAS_direct_jump 1
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #if TCG_TARGET_REG_BITS == 64
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index c9af6d592f..1337bc1f1e 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -121,7 +121,6 @@ typedef enum {
> #define TCG_TARGET_HAS_clz_i32 0
> #define TCG_TARGET_HAS_ctz_i32 0
> #define TCG_TARGET_HAS_ctpop_i32 0
> -#define TCG_TARGET_HAS_direct_jump 0
> #define TCG_TARGET_HAS_brcond2 1
> #define TCG_TARGET_HAS_setcond2 1
> #define TCG_TARGET_HAS_qemu_st8_i32 0
> diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
> index 9f5d1cf1c7..e597e47e60 100644
> --- a/tcg/s390x/tcg-target.h
> +++ b/tcg/s390x/tcg-target.h
> @@ -105,7 +105,6 @@ extern uint64_t s390_facilities[3];
> #define TCG_TARGET_HAS_mulsh_i32 0
> #define TCG_TARGET_HAS_extrl_i64_i32 0
> #define TCG_TARGET_HAS_extrh_i64_i32 0
> -#define TCG_TARGET_HAS_direct_jump 1
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #define TCG_TARGET_HAS_div2_i64 1
> diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h
> index b78a545581..1d6a5c8b07 100644
> --- a/tcg/sparc64/tcg-target.h
> +++ b/tcg/sparc64/tcg-target.h
> @@ -111,7 +111,6 @@ extern bool use_vis3_instructions;
> #define TCG_TARGET_HAS_muls2_i32 1
> #define TCG_TARGET_HAS_muluh_i32 0
> #define TCG_TARGET_HAS_mulsh_i32 0
> -#define TCG_TARGET_HAS_direct_jump 1
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #define TCG_TARGET_HAS_extrl_i64_i32 1
> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
> index 359d62c2f3..1414ab4d5b 100644
> --- a/tcg/tci/tcg-target.h
> +++ b/tcg/tci/tcg-target.h
> @@ -82,7 +82,6 @@
> #define TCG_TARGET_HAS_muls2_i32 1
> #define TCG_TARGET_HAS_muluh_i32 0
> #define TCG_TARGET_HAS_mulsh_i32 0
> -#define TCG_TARGET_HAS_direct_jump 0
> #define TCG_TARGET_HAS_qemu_st8_i32 0
>
> #if TCG_TARGET_REG_BITS == 64
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index ac5b581e52..0892c6534a 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -572,14 +572,13 @@ void cpu_exec_step_atomic(CPUState *cpu)
>
> void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr)
> {
> + const TranslationBlock *c_tb = tcg_splitwx_to_rx(tb);
> + uintptr_t offset = tb->jmp_insn_offset[n];
> + uintptr_t jmp_rx = (uintptr_t)tb->tc.ptr + offset;
> + uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff;
> +
> tb->jmp_target_addr[n] = addr;
> - if (TCG_TARGET_HAS_direct_jump) {
> - const TranslationBlock *c_tb = tcg_splitwx_to_rx(tb);
> - uintptr_t offset = tb->jmp_insn_offset[n];
> - uintptr_t jmp_rx = (uintptr_t)tb->tc.ptr + offset;
> - uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff;
> - tb_target_set_jmp_target(c_tb, n, jmp_rx, jmp_rw);
> - }
> + tb_target_set_jmp_target(c_tb, n, jmp_rx, jmp_rw);
> }
>
> static inline void tb_add_jump(TranslationBlock *tb, int n,
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 7b16af17da..9d7e2b1f1b 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -319,7 +319,6 @@ static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContext *s, int which)
> * We will check for overflow at the end of the opcode loop in
> * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX.
> */
> - tcg_debug_assert(TCG_TARGET_HAS_direct_jump);
> s->gen_tb->jmp_insn_offset[which] = tcg_current_code_size(s);
> }
>
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index b21dd561fa..e1e1c2620d 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -1945,7 +1945,6 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> intptr_t ptr, dif, dil;
> TCGReg base = TCG_REG_PC;
>
> - qemu_build_assert(!TCG_TARGET_HAS_direct_jump);
> ptr = get_jmp_target_addr(s, which);
> dif = tcg_pcrel_diff(s, (void *)ptr) - 8;
> dil = sextract32(dif, 0, 12);
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
> index 0b5e100cb1..6e000d8e69 100644
> --- a/tcg/mips/tcg-target.c.inc
> +++ b/tcg/mips/tcg-target.c.inc
> @@ -1969,7 +1969,6 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
> static void tcg_out_goto_tb(TCGContext *s, int which)
> {
> /* indirect jump method */
> - qemu_build_assert(!TCG_TARGET_HAS_direct_jump);
> tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
> get_jmp_target_addr(s, which));
> tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index e6a3915859..136fe54d4b 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1302,7 +1302,6 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
>
> static void tcg_out_goto_tb(TCGContext *s, int which)
> {
> - qemu_build_assert(!TCG_TARGET_HAS_direct_jump);
> /* indirect jump method */
> tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
> get_jmp_target_addr(s, which));
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index 2d049a4cc7..218318feb2 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -1973,6 +1973,9 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
> void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
> uintptr_t jmp_rx, uintptr_t jmp_rw)
> {
> + if (!HAVE_FACILITY(GEN_INST_EXT)) {
> + return;
> + }
Someone told me this should always be true.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
next prev parent reply other threads:[~2023-01-17 18:27 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-09 1:42 [PATCH v2 00/22] tcg: exit_tb tidy, goto_tb reorg Richard Henderson
2023-01-09 1:42 ` [PATCH v2 01/22] tcg: Split out tcg_out_exit_tb Richard Henderson
2023-01-17 17:31 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 02/22] tcg/i386: Remove unused goto_tb code for indirect jump Richard Henderson
2023-01-17 17:46 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 03/22] tcg/ppc: " Richard Henderson
2023-01-17 17:46 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 04/22] tcg/sparc64: " Richard Henderson
2023-01-17 17:47 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 05/22] tcg: Replace asserts on tcg_jmp_insn_offset Richard Henderson
2023-01-17 17:48 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 06/22] tcg: Introduce set_jmp_insn_offset Richard Henderson
2023-01-17 17:49 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 07/22] tcg: Introduce get_jmp_target_addr Richard Henderson
2023-01-17 17:51 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 08/22] tcg: Split out tcg_out_goto_tb Richard Henderson
2023-01-17 17:56 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 09/22] tcg: Rename TB_JMP_RESET_OFFSET_INVALID to TB_JMP_OFFSET_INVALID Richard Henderson
2023-01-17 17:57 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 10/22] tcg: Add gen_tb to TCGContext Richard Henderson
2023-01-17 17:58 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 11/22] tcg: Add TranslationBlock.jmp_insn_offset Richard Henderson
2023-01-17 18:01 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 12/22] tcg: Change tb_target_set_jmp_target arguments Richard Henderson
2023-01-17 18:05 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 13/22] tcg: Move tb_target_set_jmp_target declaration to tcg.h Richard Henderson
2023-01-17 18:10 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 14/22] tcg: Always define tb_target_set_jmp_target Richard Henderson
2023-01-17 18:14 ` Alex Bennée
2023-01-17 19:51 ` Richard Henderson
2023-01-09 1:42 ` [PATCH v2 15/22] tcg: Remove TCG_TARGET_HAS_direct_jump Richard Henderson
2023-01-17 18:25 ` Alex Bennée [this message]
2023-01-09 1:42 ` [PATCH v2 16/22] tcg/aarch64: Reorg goto_tb implementation Richard Henderson
2023-01-17 18:26 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 17/22] tcg/ppc: " Richard Henderson
2023-01-17 18:30 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 18/22] tcg/sparc64: Remove USE_REG_TB Richard Henderson
2023-01-17 18:31 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 19/22] tcg/sparc64: Reorg goto_tb implementation Richard Henderson
2023-01-17 18:33 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 20/22] tcg/arm: Implement direct branch for goto_tb Richard Henderson
2023-01-17 18:33 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 21/22] tcg/riscv: Introduce OPC_NOP Richard Henderson
2023-01-17 18:35 ` Alex Bennée
2023-01-09 1:42 ` [PATCH v2 22/22] tcg/riscv: Implement direct branch for goto_tb Richard Henderson
2023-01-17 18:37 ` Alex Bennée
2023-01-15 2:33 ` [PATCH v2 00/22] tcg: exit_tb tidy, goto_tb reorg Richard Henderson
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