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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Thomas Huth <thuth@redhat.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Ben Widawsky <ben.widawsky@intel.com>,
	Marcel  Apfelbaum <marcel.apfelbaum@gmail.com>,
	qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [PULL 02/10] pci-bridge/cxl_downstream: Add a CXL switch downstream port
Date: Mon, 05 Dec 2022 14:59:39 +0000	[thread overview]
Message-ID: <87y1rlnb28.fsf@linaro.org> (raw)
In-Reply-To: <20221205124516.00006362@huawei.com>


Jonathan Cameron via <qemu-devel@nongnu.org> writes:

> On Mon, 5 Dec 2022 10:54:03 +0000
> Jonathan Cameron via <qemu-devel@nongnu.org> wrote:
>
>> On Sun, 4 Dec 2022 08:23:55 +0100
>> Thomas Huth <thuth@redhat.com> wrote:
>> 
>> > On 04/11/2022 07.47, Thomas Huth wrote:  
>> > > On 16/06/2022 18.57, Michael S. Tsirkin wrote:    
>> > >> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> > >>
>> > >> Emulation of a simple CXL Switch downstream port.
>> > >> The Device ID has been allocated for this use.
>> > >>
>> > >> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> > >> Message-Id: <20220616145126.8002-3-Jonathan.Cameron@huawei.com>
>> > >> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>> > >> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
>> > >> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>> > >> ---
>> > >>   hw/cxl/cxl-host.c              |  43 +++++-
>> > >>   hw/pci-bridge/cxl_downstream.c | 249 +++++++++++++++++++++++++++++++++
>> > >>   hw/pci-bridge/meson.build      |   2 +-
>> > >>   3 files changed, 291 insertions(+), 3 deletions(-)
>> > >>   create mode 100644 hw/pci-bridge/cxl_downstream.c    
>> > > 
>> > >   Hi!
>> > > 
>> > > There is a memory problem somewhere in this new device. I can make QEMU 
>> > > crash by running something like this:
>> > > 
>> > > $ MALLOC_PERTURB_=59 ./qemu-system-x86_64 -M x-remote \
>> > >      -display none -monitor stdio
>> > > QEMU 7.1.50 monitor - type 'help' for more information
>> > > (qemu) device_add cxl-downstream
>> > > ./qemu/qom/object.c:1188:5: runtime error: member access within misaligned 
>> > > address 0x3b3b3b3b3b3b3b3b for type 'struct Object', which requires 8 byte 
>> > > alignment
>> > > 0x3b3b3b3b3b3b3b3b: note: pointer points here
>> > > <memory cannot be printed>
>> > > Bus error (core dumped)
>> > > 
>> > > Could you have a look if you've got some spare minutes?    
>> > 
>> > Ping! Jonathan, Michael, any news on this bug?
>> > 
>> > (this breaks one of my local tests, that's why it's annoying for me)  
>> Sorry, my email filters ate your earlier message.
>> 
>> Looking into this now. I'll note that it also happens on
>> device_add xio3130-downstream so not specific to this new device.
>> 
>> So far all I've managed to do is track it to something rcu related
>> as failing in a call to drain_call_rcu() in qmp_device_add()
>> 
>> Will continue digging.
>
> Assuming I'm seeing the same thing...
>
> Problem is g_free() on the PCIBridge windows: 
> https://elixir.bootlin.com/qemu/latest/source/hw/pci/pci_bridge.c#L235
>
> Is called before we get an rcu_call() to flatview_destroy() as a
> result of the final call of flatview_unref() in address_space_set_flatview()
> so we get a use after free.
>
> As to what the fix is...  Suggestions welcome!

It sounds like this is the wrong place to free the value then. I guess
the PCI aliases into &w->alias_io() don't get dealt with until RCU
clean-up time.

I *think* using g_free_rcu() should be enough to ensure the free occurs
after the rest of the RCU cleanups but maybe you should only be cleaning
up the windows at device unrealize time? Is this a dynamic piece of
memory which gets updated during the lifetime of the device?

If the memory is being cleared with RCU then the access to the base
pointer should be done with the appropriate qatomic_rcu_[set|read]
functions.

-- 
Alex Bennée


  reply	other threads:[~2022-12-05 15:09 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-16 16:57 [PULL 00/10] virtio,pc,pci: fixes,cleanups,features Michael S. Tsirkin
2022-06-16 16:57 ` [PULL 01/10] pci-bridge/cxl_upstream: Add a CXL switch upstream port Michael S. Tsirkin
2022-06-16 16:57 ` [PULL 02/10] pci-bridge/cxl_downstream: Add a CXL switch downstream port Michael S. Tsirkin
2022-11-04  6:47   ` Thomas Huth
2022-12-04  7:23     ` Thomas Huth
2022-12-05 10:54       ` Jonathan Cameron via
2022-12-05 12:45         ` Jonathan Cameron via
2022-12-05 14:59           ` Alex Bennée [this message]
2022-12-07 13:21             ` Jonathan Cameron via
2022-12-07 13:26               ` Thomas Huth
2023-03-24 10:17                 ` Thomas Huth
2023-04-03 16:12                   ` Jonathan Cameron via
2022-06-16 16:57 ` [PULL 03/10] docs/cxl: Add switch documentation Michael S. Tsirkin
2022-06-16 16:57 ` [PULL 04/10] virtio/vhost-user: Fix wrong vhost notifier GPtrArray size Michael S. Tsirkin
2022-06-16 16:57 ` [PULL 05/10] virtio-iommu: Add bypass mode support to assigned device Michael S. Tsirkin
2022-06-16 16:57 ` [PULL 06/10] virtio-iommu: Use recursive lock to avoid deadlock Michael S. Tsirkin
2022-06-16 16:57 ` [PULL 07/10] virtio-iommu: Add an assert check in translate routine Michael S. Tsirkin
2022-06-16 16:57 ` [PULL 08/10] crypto: Introduce RSA algorithm Michael S. Tsirkin
2022-06-16 16:57 ` [PULL 09/10] vhost: also check queue state in the vhost_dev_set_log error routine Michael S. Tsirkin
2022-06-16 16:57 ` [PULL 10/10] acpi/erst: fix fallthrough code upon validation failure Michael S. Tsirkin
2022-06-16 20:46 ` [PULL 00/10] virtio,pc,pci: fixes,cleanups,features Richard Henderson

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