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Mon, 11 Oct 2021 23:41:48 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 814F01FF96; Tue, 12 Oct 2021 07:41:47 +0100 (BST) References: <20211011185332.166763-1-richard.henderson@linaro.org> User-agent: mu4e 1.7.0; emacs 28.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Subject: Re: [PATCH] target/s390x: move tcg_gen_insn_start to s390x_tr_insn_start Date: Tue, 12 Oct 2021 07:41:20 +0100 In-reply-to: <20211011185332.166763-1-richard.henderson@linaro.org> Message-ID: <87y26ywxqs.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > We use INDEX_op_insn_start to make the start of instruction boundaries. > If we don't do it in the .insn_start hook things get confused especially > now plugins want to use that marking to identify the start of instructions > and will bomb out if it sees instrumented ops before the first instruction > boundary. > > Signed-off-by: Richard Henderson Well that is considerably simpler than my patch... I'll apply it to the PR and resubmit ;-) Reviewed-by: Alex Benn=C3=A9e > --- > target/s390x/tcg/translate.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c > index f284870cd2..a2d6fa5cca 100644 > --- a/target/s390x/tcg/translate.c > +++ b/target/s390x/tcg/translate.c > @@ -138,6 +138,7 @@ struct DisasFields { > struct DisasContext { > DisasContextBase base; > const DisasInsn *insn; > + TCGOp *insn_start; > DisasFields fields; > uint64_t ex_value; > /* > @@ -6380,8 +6381,8 @@ static DisasJumpType translate_one(CPUS390XState *e= nv, DisasContext *s) > /* Search for the insn in the table. */ > insn =3D extract_insn(env, s); >=20=20 > - /* Emit insn_start now that we know the ILEN. */ > - tcg_gen_insn_start(s->base.pc_next, s->cc_op, s->ilen); > + /* Update insn_start now that we know the ILEN. */ > + tcg_set_insn_start_param(s->insn_start, 2, s->ilen); >=20=20 > /* Not found means unimplemented/illegal opcode. */ > if (insn =3D=3D NULL) { > @@ -6552,6 +6553,11 @@ static void s390x_tr_tb_start(DisasContextBase *db= , CPUState *cs) >=20=20 > static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) > { > + DisasContext *dc =3D container_of(dcbase, DisasContext, base); > + > + /* Delay the set of ilen until we've read the insn. */ > + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); > + dc->insn_start =3D tcg_last_op(); > } >=20=20 > static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cs) --=20 Alex Benn=C3=A9e