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Fri, 12 Feb 2021 08:02:12 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id w4sm14177962wmc.13.2021.02.12.08.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Feb 2021 08:02:11 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1C04E1FF7E; Fri, 12 Feb 2021 16:02:11 +0000 (GMT) References: <20210210221053.18050-1-alex.bennee@linaro.org> <20210210221053.18050-21-alex.bennee@linaro.org> <877dndz6p7.fsf@linaro.org> User-agent: mu4e 1.5.8; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Aaron Lindsay Subject: Re: [PATCH v2 20/21] accel/tcg: allow plugin instrumentation to be disable via cflags Date: Fri, 12 Feb 2021 16:00:37 +0000 In-reply-to: <877dndz6p7.fsf@linaro.org> Message-ID: <87y2ftxojg.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-devel@nongnu.org, robhenry@microsoft.com, mahmoudabdalghany@outlook.com, cota@braap.org, Paolo Bonzini , kuhn.chenqun@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Alex Benn=C3=A9e writes: > Aaron Lindsay writes: > >> On Feb 10 22:10, Alex Benn=C3=A9e wrote: >>> When icount is enabled and we recompile an MMIO access we end up >>> double counting the instruction execution. To avoid this we introduce >>> the CF_NOINSTR cflag which disables instrumentation for the next TB. >>> As this is part of the hashed compile flags we will only execute the >>> generated TB while coming out of a cpu_io_recompile. >> >> Unfortunately this patch works a little too well! >> >> With this change, the memory access callbacks registered via >> `qemu_plugin_register_vcpu_mem_cb()` are never called for the >> re-translated instruction making the IO access, since we've disabled all >> instrumentation. >> >> Is it possible to selectively disable only instruction callbacks using >> this mechanism, while still allowing others that would not yet have been >> called for the re-translated instruction? > > Can you try the following fugly patch on top of this series: > > @@ -120,8 +128,13 @@ void qemu_plugin_register_vcpu_mem_cb(struct qemu_pl= ugin_insn *insn, > enum qemu_plugin_mem_rw rw, > void *udata) > { > - plugin_register_vcpu_mem_cb(&insn->cbs[PLUGIN_CB_MEM][PLUGIN_CB_REGU= LAR], > - cb, flags, rw, udata); > + if (insn->store_only && (rw & QEMU_PLUGIN_MEM_W)) { > + plugin_register_vcpu_mem_cb(&insn->cbs[PLUGIN_CB_MEM][PLUGIN_CB_= REGULAR], > + cb, flags, QEMU_PLUGIN_MEM_W, udata); > + } else { > + plugin_register_vcpu_mem_cb(&insn->cbs[PLUGIN_CB_MEM][PLUGIN_CB_= REGULAR], > + cb, flags, rw, udata); > + } > } Actually I'm wondering if I've got my sense the wrong way around. Should it be loads only: void qemu_plugin_register_vcpu_mem_cb(struct qemu_plugin_insn *insn, qemu_plugin_vcpu_mem_cb_t cb, enum qemu_plugin_cb_flags flags, enum qemu_plugin_mem_rw rw, void *udata) { if (insn->store_only && (rw & QEMU_PLUGIN_MEM_R)) { plugin_register_vcpu_mem_cb(&insn->cbs[PLUGIN_CB_MEM][PLUGIN_CB_R= EGULAR], cb, flags, QEMU_PLUGIN_MEM_R, udata); } else { plugin_register_vcpu_mem_cb(&insn->cbs[PLUGIN_CB_MEM][PLUGIN_CB_R= EGULAR], cb, flags, rw, udata); } } obviously I'd have to rename the variables :-/ --=20 Alex Benn=C3=A9e