From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43913) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fLRL4-0006GA-VE for qemu-devel@nongnu.org; Wed, 23 May 2018 06:49:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fLRL0-0002nO-VK for qemu-devel@nongnu.org; Wed, 23 May 2018 06:49:51 -0400 Received: from mail-wm0-x243.google.com ([2a00:1450:400c:c09::243]:51871) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fLRL0-0002mi-N0 for qemu-devel@nongnu.org; Wed, 23 May 2018 06:49:46 -0400 Received: by mail-wm0-x243.google.com with SMTP id j4-v6so7732465wme.1 for ; Wed, 23 May 2018 03:49:46 -0700 (PDT) References: <20180521140402.23318-1-peter.maydell@linaro.org> <20180521140402.23318-21-peter.maydell@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <20180521140402.23318-21-peter.maydell@linaro.org> Date: Wed, 23 May 2018 11:49:43 +0100 Message-ID: <87y3gatznc.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 20/27] hw/misc/tz-mpc.c: Implement correct blocked-access behaviour List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org, Paolo Bonzini , Richard Henderson Peter Maydell writes: > The MPC is guest-configurable for whether blocked accesses: > * should be RAZ/WI or cause a bus error > * should generate an interrupt or not > > Implement this behaviour in the blocked-access handlers. > > Signed-off-by: Peter Maydell > --- > hw/misc/tz-mpc.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 48 insertions(+), 2 deletions(-) > > diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c > index 93453cbef2..39a72563b7 100644 > --- a/hw/misc/tz-mpc.c > +++ b/hw/misc/tz-mpc.c > @@ -43,6 +43,9 @@ REG32(INT_EN, 0x28) > FIELD(INT_EN, IRQ, 0, 1) > REG32(INT_INFO1, 0x2c) > REG32(INT_INFO2, 0x30) > + FIELD(INT_INFO2, HMASTER, 0, 16) > + FIELD(INT_INFO2, HNONSEC, 16, 1) > + FIELD(INT_INFO2, CFG_NS, 17, 1) > REG32(INT_SET, 0x34) > FIELD(INT_SET, IRQ, 0, 1) > REG32(PIDR4, 0xfd0) > @@ -266,6 +269,45 @@ static const MemoryRegionOps tz_mpc_reg_ops =3D { > .impl.max_access_size =3D 4, > }; > > +static inline bool tz_mpc_cfg_ns(TZMPC *s, hwaddr addr) > +{ > + /* Return the cfg_ns bit from the LUT for the specified address */ > + hwaddr blknum =3D addr / s->blocksize; > + hwaddr blkword =3D blknum / 32; > + uint32_t blkbit =3D 1U << (blknum % 32); > + > + /* This would imply the address was larger than the size we > + * defined this memory region to be, so it can't happen. > + */ > + assert(blkword < s->blk_max); > + return s->blk_lut[blkword] & blkbit; > +} > + > +static MemTxResult tz_mpc_handle_block(TZMPC *s, hwaddr addr, MemTxAttrs= attrs) > +{ > + /* Handle a blocked transaction: raise IRQ, capture info, etc */ > + if (!s->int_stat) { > + /* First blocked transfer: capture information into INT_INFO1 and > + * INT_INFO2. Subsequent transfers are still blocked but don't > + * capture information until the guest clears the interrupt. > + */ > + > + s->int_info1 =3D addr; > + s->int_info2 =3D 0; > + s->int_info2 =3D FIELD_DP32(s->int_info2, INT_INFO2, HMASTER, > + attrs.requester_id & 0xffff); Does this actually need masking given the source is a 16 bit wide bitfield? > + s->int_info2 =3D FIELD_DP32(s->int_info2, INT_INFO2, HNONSEC, > + ~attrs.secure); > + s->int_info2 =3D FIELD_DP32(s->int_info2, INT_INFO2, CFG_NS, > + tz_mpc_cfg_ns(s, addr)); > + s->int_stat |=3D R_INT_STAT_IRQ_MASK; > + tz_mpc_irq_update(s); > + } > + > + /* Generate bus error if desired; otherwise RAZ/WI */ > + return (s->ctrl & R_CTRL_SEC_RESP_MASK) ? MEMTX_ERROR : MEMTX_OK; > +} > + > /* Accesses only reach these read and write functions if the MPC is > * blocking them; non-blocked accesses go directly to the downstream > * memory region without passing through this code. > @@ -274,19 +316,23 @@ static MemTxResult tz_mpc_mem_blocked_read(void *op= aque, hwaddr addr, > uint64_t *pdata, > unsigned size, MemTxAttrs att= rs) > { > + TZMPC *s =3D TZ_MPC(opaque); > + > trace_tz_mpc_mem_blocked_read(addr, size, attrs.secure); > > *pdata =3D 0; > - return MEMTX_OK; > + return tz_mpc_handle_block(s, addr, attrs); > } > > static MemTxResult tz_mpc_mem_blocked_write(void *opaque, hwaddr addr, > uint64_t value, > unsigned size, MemTxAttrs at= trs) > { > + TZMPC *s =3D TZ_MPC(opaque); > + > trace_tz_mpc_mem_blocked_write(addr, value, size, attrs.secure); > > - return MEMTX_OK; > + return tz_mpc_handle_block(s, addr, attrs); > } > > static const MemoryRegionOps tz_mpc_mem_blocked_ops =3D { -- Alex Benn=C3=A9e