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Thu, 30 May 2024 01:33:06 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id AB6665F77F; Thu, 30 May 2024 09:33:05 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Cord Amfmgm Cc: Peter Maydell , qemu-devel@nongnu.org Subject: Re: hw/usb/hcd-ohci: Fix #1510, #303: pid not IN or OUT In-Reply-To: (Cord Amfmgm's message of "Wed, 29 May 2024 23:54:18 -0500") References: Date: Thu, 30 May 2024 09:33:05 +0100 Message-ID: <87zfs7d7i6.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Cord Amfmgm writes: > On Tue, May 28, 2024 at 11:32=E2=80=AFAM Peter Maydell wrote: > > On Tue, 28 May 2024 at 16:37, Cord Amfmgm wrote: > > > > On Tue, May 28, 2024 at 9:03=E2=80=AFAM Peter Maydell wrote: > >> > >> On Mon, 20 May 2024 at 23:24, Cord Amfmgm wrote: > >> > On Mon, May 20, 2024 at 12:05=E2=80=AFPM Peter Maydell wrote: > >> > And here's an example buffer of length 0 -- you probably already kn= ow what I'm going to do here: > >> > > >> > char buf[0]; > >> > char * CurrentBufferPointer =3D &buf[0]; > >> > char * BufferEnd =3D &buf[-1]; // "address of the last byte in the = buffer" > >> > // The OHCI Host Controller than advances CurrentBufferPointer like= this: CurrentBufferPointer +=3D 0 > >> > // After the transfer: > >> > // CurrentBufferPointer =3D &buf[0]; > >> > // BufferEnd =3D &buf[-1]; > >> > >> Right, but why do you think this is valid, rather than > >> being a guest software bug? My reading of the spec is that it's > >> pretty clear about how to say "zero length buffer", and this > >> isn't it. > >> > >> Is there some real-world guest OS that programs the OHCI > >> controller this way that we're trying to accommodate? > > > > > > qemu versions 4.2 and before allowed this behavior. > > So? That might just mean we had a bug and we fixed it. > 4.2 is a very old version of QEMU and nobody seems to have > complained in the four years since we released 5.0 about this, > which suggests that generally guest OS drivers don't try > to send zero-length buffers in this way. > > > I don't think it's valid to ask for a *popular* guest OS as a proof-of= -concept because I'm not an expert on those. > > I didn't ask for "popular"; I asked for "real-world". > What is the actual guest code you're running that falls over > because of the behaviour change? > > More generally, why do you want this behaviour to be > changed? Reasonable reasons might include: > * we're out of spec based on reading the documentation > * you're trying to run some old Windows VM/QNX/etc image, > and it doesn't work any more > * all the real hardware we tested behaves this way > > But don't necessarily include: > * something somebody wrote and only tested on QEMU happens to > assume the old behaviour rather than following the hw spec > > QEMU occasionally works around guest OS bugs, but only as > when we really have to. It's usually better to fix the > bug in the guest. > > It's not, and I've already demonstrated that real hardware is consistent = with the fix in this patch. > > Please check your tone. I don't think that is a particularly helpful comment for someone who is taking the time to review your patches. Reading through the thread I didn't see anything that said this is how real HW behaves but I may well have missed it. However you have a number of review comments to address so I suggest you spin a v2 of the series to address them and outline the reason to accept an out of spec transaction. --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro