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Sat, 03 Feb 2024 05:58:34 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 50CC85F7A9; Sat, 3 Feb 2024 13:58:34 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Akihiko Odaki Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Mikhail Tyutin , Aleksandr Anenkov , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Fabiano Rosas , Andrew Jones , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v11 0/3] gdbstub and TCG plugin improvements In-Reply-To: (Akihiko Odaki's message of "Sat, 3 Feb 2024 20:26:37 +0900") References: <20240203-riscv-v11-0-a23f4848a628@daynix.com> <87bk8xpzyl.fsf@draig.linaro.org> User-Agent: mu4e 1.11.27; emacs 29.1 Date: Sat, 03 Feb 2024 13:58:34 +0000 Message-ID: <87zfwhodit.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Akihiko Odaki writes: > On 2024/02/03 20:08, Alex Benn=C3=A9e wrote: >> Akihiko Odaki writes: >>=20 >>> This series extracts fixes and refactorings that can be applied >>> independently from "[PATCH v9 00/23] plugins: Allow to read registers". >>> >>> The patch "target/riscv: Move MISA limits to class" was replaced with >>> patch "target/riscv: Move misa_mxl_max to class" since I found instances >>> may have different misa_ext_mask. >> As this is re-based on Alistair's riscv-to-apply.next tree I'll wait >> for >> this to go through the RiscV trees and then re-base the plugin patches >> and dropping the merged riscv patches from my tree. >> In the meantime feel free to review: >> Message-Id: <20240122145610.413836-1-alex.bennee@linaro.org> >> Date: Mon, 22 Jan 2024 14:55:49 +0000 >> Subject: [PATCH v3 00/21] plugin updates (register access) for 9.0 (p= re-PR?) >> From: =3D?UTF-8?q?Alex=3D20Benn=3DC3=3DA9e?=3D >> For: >> contrib/plugins: extend execlog to track register changes >> gdbstub: expose api to find registers >> So I can add this to my maintainer omnibus series for the next PR I >> send. > > I added one trivial comment to: "gdbstub: expose api to find registers" > > "contrib/plugins: extend execlog to track register changes" depends on > "plugins: add an API to read registers". The comments for the patch in > the following email are not addressed yet: > https://lore.kernel.org/all/4b2156ed-688d-4617-b52d-200413f01156@daynix.c= om/ I don't think we need to serialise with the BQL as the structures are per-CPU (and created on vCPU creation). As far as the restructuring we can move it into gdbstub later if there is a need to. At the moment the structure is just housekeeping for plugins. > > Please check them out. --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro