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Thu, 21 Apr 2022 09:48:23 +0100 (BST) References: <20220418191100.270334-1-leandro.lupori@eldorado.org.br> <20220418191100.270334-3-leandro.lupori@eldorado.org.br> <962f7ef4-7dcc-fb5d-5e55-90eb3ba65e47@linaro.org> User-agent: mu4e 1.7.13; emacs 28.1.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Subject: Re: [RFC PATCH v3 2/5] ppc64: Fix semihosting on ppc64le Date: Thu, 21 Apr 2022 09:46:30 +0100 In-reply-to: <962f7ef4-7dcc-fb5d-5e55-90eb3ba65e47@linaro.org> Message-ID: <87zgkevn3c.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Leandro Lupori , danielhb413@gmail.com, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, pbonzini@redhat.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > On 4/20/22 12:42, Peter Maydell wrote: >> On Mon, 18 Apr 2022 at 20:19, Leandro Lupori >> wrote: >>> >>> PPC64 CPUs can change its endian dynamically, so semihosting code >>> must check its MSR at run time to determine if byte swapping is >>> needed. >> Arm CPUs also change endianness dynamically, so why is this >> change PPC-specific ? > > I'm reasonably certain that we simply don't test armbe or aarch64_be > semihosting. Leandro found this because qemu-system-ppc64 defaults to > BE and qemu-system-aarch64 defaults to LE. Maybe it is time to have a generic endianess variable in CPUState so we can avoid having arch specific hacks in the semihosting code. That said is endianess binary? I seem to recall on ARM the instruction stream is always in one endianess so it only really affects CPU data loads and stores. Is it the same for PPC? > > > r~ --=20 Alex Benn=C3=A9e