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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f25915719sm14344352f8f.60.2025.02.17.23.24.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Feb 2025 23:24:36 -0800 (PST) Message-ID: <88169d47-f3a1-4dbe-aa9e-9ca3617adca8@redhat.com> Date: Tue, 18 Feb 2025 08:24:33 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/5] Fix vIOMMU reset order Content-Language: en-US To: "Duan, Zhenzhong" , "eric.auger.pro@gmail.com" , "qemu-devel@nongnu.org" , "qemu-arm@nongnu.org" , "peter.maydell@linaro.org" , "mst@redhat.com" , "jasowang@redhat.com" , "imammedo@redhat.com" , "peterx@redhat.com" , "alex.williamson@redhat.com" , "clg@redhat.com" , "philmd@linaro.org" , "ddutile@redhat.com" References: <20250217133746.6801-1-eric.auger@redhat.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Zhenzhong, On 2/18/25 4:32 AM, Duan, Zhenzhong wrote: > Hi Eric, > >> -----Original Message----- >> From: Eric Auger >> Subject: [PATCH v2 0/5] Fix vIOMMU reset order >> >> With current reset scheme, DMA capable devices are reset before > s/before/after ugh definitively! :-) > >> the vIOMMU which translate them. This holds for the different >> IOMMUs and various DMA capable devices such as virtio devices >> and VFIO ones. With virtio devices spurious traces can be >> observed at qemu level such as "virtio: zero sized buffers are >> not allowed" while for VFIO devices, translation faults can be >> observed at host level. >> >> Virtio devices use 3 phase reset and virtio-pci devices are reset >> in the 'hold' phase. VFIO device reset are registered using >> qemu_register_reset() and as a consequence they are also reset >> on 'hold' phase. >> >> Note that the tree of QOM devices resets depth-first but it does >> so while enforcing the 3 phases. First the tree is traversed doing >> the 'enter' phase, then the 'hold' phase and eventually the 'exit' >> phase. >> >> However the QOM hierarchy is not built so that vIOMMUs get reset >> before the DMA capable devices (IOMMUs are using either legacy reset > s/before/after > >> scheme or hold phase). Changing the QOM hierarchy does not sound >> trivial while forcing the vIOMMUs to be reset on 'exit' phase >> sounds reasonable and much simpler. Obviously this relies on the >> assumption that all DMA capable devices quiesce their DMA before >> (ie. during 'enter' or hold' phase). >> >> This was tested with qmp system_reset and virsh reset. > For the whole series, > > Reviewed-by: Zhenzhong Duan Thanks! Eric > > Thanks > Zhenzhong