RE: Instruction virtual address in TCG Plugins

[Mikhail Tyutin <m.tyutin@yadro.com>]

> > 1. Memory IO operations force TCG to create special translation blocks to
> > process that memory load/store operation. The plugin gets notification for
> > this translation block as well, but instrumentation callbacks other than
> > memory ones are silently ignored. To make it correct, the plugin has to match
> > instruction execution callback from previous TB to memory callback from that
> > special TB. The fix was to expose internal ‘memOnly’ TB flag to the plugin to
> > handle such TBs differently.
> 
> Are you talking about the CF_MEMI_ONLY compile flag? We added this to
> avoid double counting executed instructions. Has there been a clash with
> the other changes to always cpu_recompile_io? This was a change added to
> fix: https://gitlab.com/qemu-project/qemu/-/issues/1866

Yes, that's it. qemu_plugin_tb structure has 'mem_only' field for those block.
I only added API to read this flag by a plugin.

 
> > 2. Another problem is related to interrupts handling. Since we can insert pre-
> > callback on instructions only, the plugin is not aware if instruction is
> > actually executed or interrupted by an interrupt or exception. In fact, it
> > mistakenly interprets all interrupted instructions as executed. Adding API
> > to receive interrupt notification and appropriate handling of it fixes
> > the problem.
> 
> We don't process any interrupts until the start of each block so no
> asynchronous IRQs should interrupt execution. However it is possible
> that any given instruction could generate a synchronous exception so if
> you need a precise count of execution you need to instrument every
> single instruction. With enough knowledge the plugin could avoid
> instrumenting stuff that will never fault but that relies on baking
> additional knowledge into the plugin.
> 
> Generally its only memory operations that can fault (although I guess
> FPU and some more esoteric integer ops can).

That matches my observation. I do see interrupts either on TB boundary
(e.g. timers) or memory load instructions.