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[88.21.205.47]) by smtp.gmail.com with ESMTPSA id a7sm7189589wmj.12.2020.02.27.05.31.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Feb 2020 05:31:24 -0800 (PST) Subject: Re: [PATCH v2 2/2] hw/arm/armv7m: Downgrade CPU reset handler priority To: Stephanos Ioannidis , Alistair Francis References: <20200227115005.66349-1-root@stephanos.io> <20200227115005.66349-3-root@stephanos.io> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <88ad7129-9654-088d-6569-066949973a86@redhat.com> Date: Thu, 27 Feb 2020 14:31:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200227115005.66349-3-root@stephanos.io> Content-Language: en-US X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:ARM TCG CPUs" , "open list:All patches CC here" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Stephanos, On 2/27/20 12:51 PM, Stephanos Ioannidis wrote: > The ARMv7-M CPU reset handler, which loads the initial SP and PC > register values from the vector table, is currently executed before > the ROM reset handler (rom_reset), and this causes the devices that > alias low memory region (e.g. STM32F405 that aliases the flash memory > located at 0x8000000 to 0x0) to load an invalid reset vector of 0 when > the kernel image is linked to be loaded at the high memory address. So we have armv7m_load_kernel -> load_elf_as -> rom_add_blob_fixed_as -> rom_add_blob -> rom_insert. arm_cpu_reset is called before rom_reset, rom_ptr is NULL, we call initial_pc = ldl_phys(cpu_as) from an empty flash. Then later rom_reset -> address_space_write_rom. I think Alistair and myself use the 'loader' device with Cortex-M boards and never hit this problem. > > For instance, it is norm for the STM32F405 firmware ELF image to have > the text and rodata sections linked at 0x8000000, as this facilitates > proper image loading by the firmware burning utility, and the processor > can execute in place from the high flash memory address region as well. > > In order to resolve this issue, this commit downgrades the ARMCPU reset > handler invocation priority level to -1 such that it is always executed > after the ROM reset handler, which has a priority level of 0. > > Signed-off-by: Stephanos Ioannidis > --- > hw/arm/armv7m.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c > index 7531b97ccd..8b7c4b12a6 100644 > --- a/hw/arm/armv7m.c > +++ b/hw/arm/armv7m.c > @@ -352,7 +352,8 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) > * way A-profile does it. Note that this means that every M profile > * board must call this function! > */ > - qemu_register_reset(armv7m_reset, cpu); > + qemu_register_reset_with_priority( > + QEMU_RESET_PRIORITY_LEVEL(-1), armv7m_reset, cpu); > } > > static Property bitband_properties[] = { >