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Wed, 16 Apr 2025 12:13:49 -0700 (PDT) Received: from [192.168.1.87] ([38.41.223.211]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73bd219bf3dsm11180102b3a.16.2025.04.16.12.13.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Apr 2025 12:13:48 -0700 (PDT) Message-ID: <88e3297d-92c3-4a6d-a35c-dfb7e3d73a82@linaro.org> Date: Wed, 16 Apr 2025 12:13:48 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 134/163] tcg/aarch64: Remove support for add2/sub2 Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20250415192515.232910-1-richard.henderson@linaro.org> <20250415192515.232910-135-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20250415192515.232910-135-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/15/25 12:24, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/aarch64/tcg-target-con-set.h | 1 - > tcg/aarch64/tcg-target-has.h | 8 ++-- > tcg/aarch64/tcg-target.c.inc | 75 -------------------------------- > 3 files changed, 4 insertions(+), 80 deletions(-) > > diff --git a/tcg/aarch64/tcg-target-con-set.h b/tcg/aarch64/tcg-target-con-set.h > index 02a0be66fd..d0622e65fb 100644 > --- a/tcg/aarch64/tcg-target-con-set.h > +++ b/tcg/aarch64/tcg-target-con-set.h > @@ -36,4 +36,3 @@ C_O1_I2(w, w, wZ) > C_O1_I3(w, w, w, w) > C_O1_I4(r, r, rC, rz, rz) > C_O2_I1(r, r, r) > -C_O2_I4(r, r, rz, rz, rA, rMZ) > diff --git a/tcg/aarch64/tcg-target-has.h b/tcg/aarch64/tcg-target-has.h > index 011a91c263..695effd77c 100644 > --- a/tcg/aarch64/tcg-target-has.h > +++ b/tcg/aarch64/tcg-target-has.h > @@ -13,13 +13,13 @@ > #define have_lse2 (cpuinfo & CPUINFO_LSE2) > > /* optional instructions */ > -#define TCG_TARGET_HAS_add2_i32 1 > -#define TCG_TARGET_HAS_sub2_i32 1 > +#define TCG_TARGET_HAS_add2_i32 0 > +#define TCG_TARGET_HAS_sub2_i32 0 > #define TCG_TARGET_HAS_extr_i64_i32 0 > #define TCG_TARGET_HAS_qemu_st8_i32 0 > > -#define TCG_TARGET_HAS_add2_i64 1 > -#define TCG_TARGET_HAS_sub2_i64 1 > +#define TCG_TARGET_HAS_add2_i64 0 > +#define TCG_TARGET_HAS_sub2_i64 0 > > /* > * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load, > diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc > index 9dc6bf3e3d..75cf490fd2 100644 > --- a/tcg/aarch64/tcg-target.c.inc > +++ b/tcg/aarch64/tcg-target.c.inc > @@ -1575,56 +1575,6 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) > tcg_out_mov(s, TCG_TYPE_I32, rd, rn); > } > > -static void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl, > - TCGReg rh, TCGReg al, TCGReg ah, > - tcg_target_long bl, tcg_target_long bh, > - bool const_bl, bool const_bh, bool sub) > -{ > - TCGReg orig_rl = rl; > - AArch64Insn insn; > - > - if (rl == ah || (!const_bh && rl == bh)) { > - rl = TCG_REG_TMP0; > - } > - > - if (const_bl) { > - if (bl < 0) { > - bl = -bl; > - insn = sub ? I3401_ADDSI : I3401_SUBSI; > - } else { > - insn = sub ? I3401_SUBSI : I3401_ADDSI; > - } > - > - if (unlikely(al == TCG_REG_XZR)) { > - /* ??? We want to allow al to be zero for the benefit of > - negation via subtraction. However, that leaves open the > - possibility of adding 0+const in the low part, and the > - immediate add instructions encode XSP not XZR. Don't try > - anything more elaborate here than loading another zero. */ > - al = TCG_REG_TMP0; > - tcg_out_movi(s, ext, al, 0); > - } > - tcg_out_insn_3401(s, insn, ext, rl, al, bl); > - } else { > - tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl); > - } > - > - insn = I3503_ADC; > - if (const_bh) { > - /* Note that the only two constants we support are 0 and -1, and > - that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */ > - if ((bh != 0) ^ sub) { > - insn = I3503_SBC; > - } > - bh = TCG_REG_XZR; > - } else if (sub) { > - insn = I3503_SBC; > - } > - tcg_out_insn_3503(s, insn, ext, rh, ah, bh); > - > - tcg_out_mov(s, ext, orig_rl, rl); > -} > - > static inline void tcg_out_mb(TCGContext *s, TCGArg a0) > { > static const uint32_t sync[] = { > @@ -2895,25 +2845,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, > tcg_out_qemu_ldst_i128(s, a0, a1, a2, args[3], false); > break; > > - case INDEX_op_add2_i32: > - tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, a2, args[3], > - (int32_t)args[4], args[5], const_args[4], > - const_args[5], false); > - break; > - case INDEX_op_add2_i64: > - tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, a2, args[3], args[4], > - args[5], const_args[4], const_args[5], false); > - break; > - case INDEX_op_sub2_i32: > - tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, a2, args[3], > - (int32_t)args[4], args[5], const_args[4], > - const_args[5], true); > - break; > - case INDEX_op_sub2_i64: > - tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, a2, args[3], args[4], > - args[5], const_args[4], const_args[5], true); > - break; > - > case INDEX_op_mb: > tcg_out_mb(s, a0); > break; > @@ -3407,12 +3338,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_qemu_st_i128: > return C_O0_I3(rz, rz, r); > > - case INDEX_op_add2_i32: > - case INDEX_op_add2_i64: > - case INDEX_op_sub2_i32: > - case INDEX_op_sub2_i64: > - return C_O2_I4(r, r, rz, rz, rA, rMZ); > - > case INDEX_op_add_vec: > case INDEX_op_sub_vec: > case INDEX_op_mul_vec: Reviewed-by: Pierrick Bouvier