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[83.11.37.15]) by smtp.gmail.com with ESMTPSA id p25-20020a170906141900b00a55a5384986sm585494ejc.24.2024.05.02.06.50.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 May 2024 06:50:52 -0700 (PDT) Message-ID: <88e97ffd-f308-49db-aba6-ea3b9c308d21@linaro.org> Date: Thu, 2 May 2024 15:50:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: fix MPIDR value for ARM CPUs with SMT To: Peter Maydell Cc: Dorjoy Chowdhury , qemu-devel@nongnu.org References: <20240419183135.12276-1-dorjoychy111@gmail.com> <7c6f66bf-2610-494c-9389-b558a11f8c5f@linaro.org> From: Marcin Juszkiewicz Content-Language: pl-PL, en-GB, en-HK Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=marcin.juszkiewicz@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org W dniu 2.05.2024 o 15:13, Peter Maydell pisze: > On Thu, 2 May 2024 at 14:11, Marcin Juszkiewicz > wrote: >> >> W dniu 2.05.2024 o 15:04, Dorjoy Chowdhury pisze: >>>> Should "return" also have "(1 << 24) |" to have MT=1 set? >>>> >>>> Otherwise MPIDR_EL1 = 0x000100 can mean core0 in cluster1 or core1 in >>>> cluster0. >>>> >>>> Value 0x1000100 shows MT=1 so thread0 in core1 in cluster0. >> >>> I don't know all the details but from what I understand the >>> "arm_build_mp_afiinity" is used to set the "mp_affinity" member >>> variable which I assume is about affinity, not the whole MPIDR >>> register value. That is what I assumed because the Uniprocessor >>> indication bit(30) is being set only in the "mpidr_read_val" function. >>> In the patch, the MT bit is also being set in the "mpidr_read_val" >>> function based on the SMT status (has_smt) of the CPU. >> >> mpidr_read_val() is used only to set VMPIDR and VMPIDR_EL2 registers. >> >> So setting MT bit for MPIDR_EL1 needs to be added somewhere. > > The readfn for MPIDR_EL1 is mpidr_read(), which calls > mpidr_read_val(). My mistake. Both hw/arm/sbsa-ref.c and hw/arm/virt.c build cpu information in DeviceTree using "arm_build_mp_afinnity()" function. So if firmware parses it then it gets wrong values. Firmware should probably read MPIDR_EL1 directly instead but what with those who read DT and rely on this value already?