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From: Sairaj Kodilkar <sarunkod@amd.com>
To: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>,
	<qemu-devel@nongnu.org>
Cc: <pbonzini@redhat.com>, <richard.henderson@linaro.org>,
	<eduardo@habkost.net>, <peterx@redhat.com>, <david@redhat.com>,
	<philmd@linaro.org>, <mst@redhat.com>,
	<marcel.apfelbaum@gmail.com>, <alex.williamson@redhat.com>,
	<vasant.hegde@amd.com>, <suravee.suthikulpanit@amd.com>,
	<santosh.shukla@amd.com>, <Wei.Huang2@amd.com>,
	<clement.mathieu--drif@eviden.com>, <ethan.milon@eviden.com>,
	<joao.m.martins@oracle.com>, <boris.ostrovsky@oracle.com>
Subject: Re: [PATCH v2 05/20] amd_iommu: Add helper function to extract the DTE
Date: Mon, 12 May 2025 12:15:46 +0530	[thread overview]
Message-ID: <89aa3b2f-092f-43a4-a96c-5755cf06efb9@amd.com> (raw)
In-Reply-To: <20250502021605.1795985-6-alejandro.j.jimenez@oracle.com>



On 5/2/2025 7:45 AM, Alejandro Jimenez wrote:
> Extracting the DTE from a given AMDVIAddressSpace pointer structure is a
> common operation required for syncing the shadow page tables. Implement a
> helper to do it and check for common error conditions.
> 
> Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
> ---
>   hw/i386/amd_iommu.c | 45 ++++++++++++++++++++++++++++++++++++++++-----
>   1 file changed, 40 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
> index dff6f04c8651..5322a614f5d6 100644
> --- a/hw/i386/amd_iommu.c
> +++ b/hw/i386/amd_iommu.c
> @@ -77,6 +77,18 @@ typedef struct AMDVIIOTLBEntry {
>       uint64_t page_mask;         /* physical page size  */
>   } AMDVIIOTLBEntry;
>   
> +/*
> + * These 'fault' reasons have an overloaded meaning since they are not only
> + * intended for describing reasons that generate an IO_PAGE_FAULT as per the AMD
> + * IOMMU specification, but are also used to signal internal errors in the
> + * emulation code.
> + */
> +typedef enum AMDVIFaultReason {
> +    AMDVI_FR_DTE_RTR_ERR = 1,   /* Failure to retrieve DTE */
> +    AMDVI_FR_DTE_V,             /* DTE[V] = 0 */
> +    AMDVI_FR_DTE_TV,            /* DTE[TV] = 0 */
> +} AMDVIFaultReason;
> +
>   uint64_t amdvi_extended_feature_register(AMDVIState *s)
>   {
>       uint64_t feature = AMDVI_DEFAULT_EXT_FEATURES;
> @@ -492,6 +504,28 @@ static inline uint64_t amdvi_get_pte_entry(AMDVIState *s, uint64_t pte_addr,
>       return pte;
>   }
>   
> +static int amdvi_as_to_dte(AMDVIAddressSpace *as, uint64_t *dte)
> +{
> +    uint16_t devid = PCI_BUILD_BDF(as->bus_num, as->devfn);
> +    AMDVIState *s = as->iommu_state;
> +
> +    if (!amdvi_get_dte(s, devid, dte)) {
> +        /* Unable to retrieve DTE for devid */
> +        return -AMDVI_FR_DTE_RTR_ERR;
> +    }
> +
> +    if (!(dte[0] & AMDVI_DEV_VALID)) {
> +        /* DTE[V] not set, address is passed untranslated for devid */
> +        return -AMDVI_FR_DTE_V;
> +    }
> +
> +    if (!(dte[0] & AMDVI_DEV_TRANSLATION_VALID)) {
> +        /* DTE[TV] not set, host page table not valid for devid */
> +        return -AMDVI_FR_DTE_TV;
> +    }
> +    return 0;
> +}
> +
>   /* log error without aborting since linux seems to be using reserved bits */
>   static void amdvi_inval_devtab_entry(AMDVIState *s, uint64_t *cmd)
>   {
> @@ -1024,6 +1058,7 @@ static void amdvi_do_translate(AMDVIAddressSpace *as, hwaddr addr,
>       uint16_t devid = PCI_BUILD_BDF(as->bus_num, as->devfn);
>       AMDVIIOTLBEntry *iotlb_entry = amdvi_iotlb_lookup(s, addr, devid);
>       uint64_t entry[4];
> +    int dte_ret;
>   
>       if (iotlb_entry) {
>           trace_amdvi_iotlb_hit(PCI_BUS_NUM(devid), PCI_SLOT(devid),
> @@ -1035,13 +1070,13 @@ static void amdvi_do_translate(AMDVIAddressSpace *as, hwaddr addr,
>           return;
>       }
>   
> -    if (!amdvi_get_dte(s, devid, entry)) {
> -        return;
> -    }
> +    dte_ret = amdvi_as_to_dte(as, entry);
>   
> -    /* devices with V = 0 are not translated */
> -    if (!(entry[0] & AMDVI_DEV_VALID)) {
> +    if (dte_ret == -AMDVI_FR_DTE_V) {
> +        /* DTE[V]=0, address is passed untranslated */
>           goto out;
> +    } else if (dte_ret == -AMDVI_FR_DTE_TV) {
> +        return;
>       }
>  

Hi Alejandro,

You missed to handle -AMDVI_FR_DTE_RTR_ERR.

Regards
Sairaj Kodilkar

>       amdvi_page_walk(as, entry, ret,



  reply	other threads:[~2025-05-12  6:46 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-02  2:15 [PATCH v2 00/20] AMD vIOMMU: DMA remapping support for VFIO devices Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 01/20] memory: Adjust event ranges to fit within notifier boundaries Alejandro Jimenez
2025-05-11 18:31   ` Michael S. Tsirkin
2025-05-12  8:02   ` David Hildenbrand
2025-05-12 17:29     ` Peter Xu
2025-06-12  6:54   ` Vasant Hegde
2025-06-12 21:49     ` Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 02/20] amd_iommu: Document '-device amd-iommu' common options Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 03/20] amd_iommu: Reorder device and page table helpers Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 04/20] amd_iommu: Helper to decode size of page invalidation command Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 05/20] amd_iommu: Add helper function to extract the DTE Alejandro Jimenez
2025-05-12  6:45   ` Sairaj Kodilkar [this message]
2025-05-14 20:23     ` Alejandro Jimenez
2025-05-20 10:18   ` Ethan MILON
2025-05-21 14:49     ` Alejandro Jimenez
2025-06-12  8:31       ` Ethan MILON
2025-05-02  2:15 ` [PATCH v2 06/20] amd_iommu: Return an error when unable to read PTE from guest memory Alejandro Jimenez
2025-06-12 10:37   ` Vasant Hegde
2025-06-13 17:44     ` Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 07/20] amd_iommu: Add helpers to walk AMD v1 Page Table format Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 08/20] amd_iommu: Add a page walker to sync shadow page tables on invalidation Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 09/20] amd_iommu: Add basic structure to support IOMMU notifier updates Alejandro Jimenez
2025-05-12  6:52   ` Sairaj Kodilkar
2025-06-23 10:53   ` Sairaj Kodilkar
2025-05-02  2:15 ` [PATCH v2 10/20] amd_iommu: Sync shadow page tables on page invalidation Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 11/20] amd_iommu: Use iova_tree records to determine large page size on UNMAP Alejandro Jimenez
2025-06-11  8:29   ` Sairaj Kodilkar
2025-06-13 21:50     ` Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 12/20] amd_iommu: Unmap all address spaces under the AMD IOMMU on reset Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 13/20] amd_iommu: Add replay callback Alejandro Jimenez
2025-05-02  2:15 ` [PATCH v2 14/20] amd_iommu: Invalidate address translations on INVALIDATE_IOMMU_ALL Alejandro Jimenez
2025-05-02  2:16 ` [PATCH v2 15/20] amd_iommu: Toggle memory regions based on address translation mode Alejandro Jimenez
2025-05-12  6:52   ` Sairaj Kodilkar
2025-05-02  2:16 ` [PATCH v2 16/20] amd_iommu: Set all address spaces to default translation mode on reset Alejandro Jimenez
2025-05-29  6:16   ` Sairaj Kodilkar
2025-05-30 21:30     ` Alejandro Jimenez
2025-06-13  8:46       ` Sairaj Kodilkar
2025-06-23 22:08         ` Alejandro Jimenez
2025-05-02  2:16 ` [PATCH v2 17/20] amd_iommu: Add dma-remap property to AMD vIOMMU device Alejandro Jimenez
2025-05-02  2:16 ` [PATCH v2 18/20] amd_iommu: Toggle address translation mode on devtab entry invalidation Alejandro Jimenez
2025-06-12  8:27   ` Ethan MILON
2025-06-12 11:23     ` Sairaj Kodilkar
2025-05-02  2:16 ` [PATCH v2 19/20] amd_iommu: Do not assume passthrough translation when DTE[TV]=0 Alejandro Jimenez
2025-05-12  7:00   ` Sairaj Kodilkar
2025-05-14 21:49     ` Alejandro Jimenez
2025-05-16  8:14       ` Sairaj Kodilkar
2025-05-02  2:16 ` [PATCH v2 20/20] amd_iommu: Refactor amdvi_page_walk() to use common code for page walk Alejandro Jimenez
2025-05-11 18:34 ` [PATCH v2 00/20] AMD vIOMMU: DMA remapping support for VFIO devices Michael S. Tsirkin
2025-05-16  8:07 ` Sairaj Kodilkar
2025-05-21  2:35   ` Alejandro Jimenez
2025-05-21  6:21     ` Sairaj Kodilkar
2025-05-30 11:41 ` Michael S. Tsirkin
2025-05-30 14:39   ` Alejandro Jimenez
2025-06-02  4:49     ` Sairaj Kodilkar

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