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[189.204.159.168]) by smtp.gmail.com with ESMTPSA id r205sm2237818oig.0.2019.05.31.08.31.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 31 May 2019 08:31:30 -0700 (PDT) To: Michael Rolnik , qemu-devel@nongnu.org References: <20190530190738.22713-1-mrolnik@gmail.com> <20190530190738.22713-6-mrolnik@gmail.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <89ce6f5b-17d6-5a11-c8c6-da23f1245162@linaro.org> Date: Fri, 31 May 2019 10:31:27 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190530190738.22713-6-mrolnik@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: Re: [Qemu-devel] [PATCH RFC v20 5/8] target/avr: Add instruction translation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sarah Harris , rth@twiddle.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/30/19 2:07 PM, Michael Rolnik wrote: > + /* decode first instruction */ > + ctx.inst[0].cpc = pc_start; > + decode_opc(&ctx, &ctx.inst[0]); > + do { > + /* set curr/next PCs */ > + cpc = ctx.inst[0].cpc; > + npc = ctx.inst[0].npc; > + > + /* decode next instruction */ > + ctx.inst[1].cpc = ctx.inst[0].npc; > + decode_opc(&ctx, &ctx.inst[1]); > + > + /* translate current instruction */ > + tcg_gen_insn_start(cpc); > + num_insns++; I don't believe that this simultaneous decode of two instructions is correct. Consider if ctx.inst[0] is a branch instruction that is placed as the very last word of memory. Ordinarily, the branch would be executed and the TranslationBlock ended. However, the advance read of ctx.inst[1] will cause a read from unmapped address space (causing an exception), or read from a device (causing "Bad ram pointer" and an abort from qemu_ram_addr_from_host_nofail). I believe that the feature that you're attempting to support with this, skip the next instruction, should be handled via an internal flag bit. This would end up looking a lot like the HPPA nullify bit, or somewhat like the ARM thumb condexec_mask. I can go into specifics if needed. Such a change would also allow you to structure this code to use "exec/translator.h", which in the future will likely be mandatory. r~