* [PATCH v3 0/5] ati-vga fixes
@ 2026-03-17 23:32 BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 1/5] ati-vga: Fix colors when frame buffer endianness does not match host BALATON Zoltan
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: BALATON Zoltan @ 2026-03-17 23:32 UTC (permalink / raw)
To: qemu-devel
Cc: Gerd Hoffmann, marcandre.lureau, Chad Jablonski,
Philippe Mathieu-Daudé
v3:
- fix patch 1 to work with 8 and 16 bit modes too
- new patch 5 to fix display updates with 8 and 16 bit modes
v2:
- fix patch 4 to really avoid warnings
These are some fixes to ati-vga for 11.0.
Patch 1 fixes problem reported in
https://lists.nongnu.org/archive/html/qemu-ppc/2026-01/msg00105.html
Patch 2 fixes output from Solaris install iso
Rendering still not always correct as it uses some unimplemented
features but it's now readable. I did not test full install though.
Patch 3 fixes vram overrun errors seen with Solaris and MorphOS when
crtc offset is non-zero (this happens on MorphOS when additional
screen is opened)
Patch 4 tries to avoid Coverity warning matching what other places
already do
Patch 5 fixes dirty region tracking when guest display depth is not
the same as the host's
BALATON Zoltan (5):
ati-vga: Fix colors when frame buffer endianness does not match host
ati-vga: Also switch mode on HW cursor enable bit change
ati-vga: Do not add crtc offset to src and dst data address
ati-vga: Avoid warnings about sign extension
ati-vga: Fix display updates in non-32 bit modes
hw/display/ati.c | 9 +++++----
hw/display/ati_2d.c | 46 ++++++++++++++++++++++++++++++---------------
2 files changed, 36 insertions(+), 19 deletions(-)
--
2.41.3
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 1/5] ati-vga: Fix colors when frame buffer endianness does not match host
2026-03-17 23:32 [PATCH v3 0/5] ati-vga fixes BALATON Zoltan
@ 2026-03-17 23:32 ` BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 2/5] ati-vga: Also switch mode on HW cursor enable bit change BALATON Zoltan
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: BALATON Zoltan @ 2026-03-17 23:32 UTC (permalink / raw)
To: qemu-devel
Cc: Gerd Hoffmann, marcandre.lureau, Chad Jablonski,
Philippe Mathieu-Daudé
When writing pixels we have to take into account if the frame buffer
endianness matches the host endianness or we need to swap to correct
endianness. This caused wrong colors e.g. with PPC Linux guest that
uses big endian frame buffer when running on little endian host.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
ROP3_BLACKNESS, ROP3_WHITENESS is probably still broken with <24 bit
modes but I don't know anything that uses it so I leave it for now
because I'm not sure which palette entries should that use in 15/16
bit modes so I'm not trying to fix that without a test case
hw/display/ati_2d.c | 40 +++++++++++++++++++++++++++++-----------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c
index 37fe6c17ee..0cbbdc33f4 100644
--- a/hw/display/ati_2d.c
+++ b/hw/display/ati_2d.c
@@ -50,6 +50,7 @@ typedef struct {
bool host_data_active;
bool left_to_right;
bool top_to_bottom;
+ bool need_swap;
uint32_t frgd_clr;
const uint8_t *palette;
const uint8_t *vram_end;
@@ -89,6 +90,7 @@ static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx)
ctx->host_data_active = s->host_data.active;
ctx->left_to_right = s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT;
ctx->top_to_bottom = s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM;
+ ctx->need_swap = HOST_BIG_ENDIAN != s->vga.big_endian_fb ? true : false;
ctx->frgd_clr = s->regs.dp_brush_frgd_clr;
ctx->palette = s->vga.palette;
ctx->dst_offset = s->regs.dst_offset;
@@ -131,6 +133,17 @@ static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx)
(ctx->top_to_bottom ? 'v' : '^'));
}
+static uint32_t make_filler(int bpp, uint32_t color)
+{
+ if (bpp < 24) {
+ color |= color << 16;
+ if (bpp < 15) {
+ color |= color << 8;
+ }
+ }
+ return color;
+}
+
static bool ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_pixman)
{
QemuRect vis_src, vis_dst;
@@ -255,7 +268,7 @@ static bool ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_pixman)
switch (ctx->rop3) {
case ROP3_PATCOPY:
- filler = ctx->frgd_clr;
+ filler = make_filler(ctx->bpp, ctx->frgd_clr);
break;
case ROP3_BLACKNESS:
filler = 0xffUL << 24 | rgb_to_pixel32(ctx->palette[0],
@@ -268,10 +281,12 @@ static bool ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_pixman)
ctx->palette[5]);
break;
}
-
DPRINTF("pixman_fill(%p, %ld, %d, %d, %d, %d, %d, %x)\n",
ctx->dst_bits, ctx->dst_stride / sizeof(uint32_t), ctx->bpp,
vis_dst.x, vis_dst.y, vis_dst.width, vis_dst.height, filler);
+ if (ctx->need_swap) {
+ bswap32s(&filler);
+ }
#ifdef CONFIG_PIXMAN
if (!(use_pixman & BIT(0)) ||
!pixman_fill((uint32_t *)ctx->dst_bits,
@@ -325,11 +340,8 @@ void ati_2d_blt(ATIVGAState *s)
bool ati_host_data_flush(ATIVGAState *s)
{
ATI2DCtx ctx, chunk;
- uint32_t fg = s->regs.dp_src_frgd_clr;
- uint32_t bg = s->regs.dp_src_bkgd_clr;
unsigned bypp, pix_count, row, col, idx;
uint8_t pix_buf[ATI_HOST_DATA_ACC_BITS * sizeof(uint32_t)];
- uint32_t byte_pix_order = s->regs.dp_datatype & DP_BYTE_PIX_ORDER;
uint32_t src_source = s->regs.dp_mix & DP_SRC_SOURCE;
uint32_t src_datatype = s->regs.dp_datatype & DP_SRC_DATATYPE;
@@ -360,21 +372,27 @@ bool ati_host_data_flush(ATIVGAState *s)
}
bypp = ctx.bpp / 8;
-
+ pix_count = ATI_HOST_DATA_ACC_BITS;
if (src_datatype == SRC_COLOR) {
- pix_count = ATI_HOST_DATA_ACC_BITS / ctx.bpp;
- memcpy(pix_buf, &s->host_data.acc[0], sizeof(s->host_data.acc));
+ pix_count /= ctx.bpp;
+ memcpy(pix_buf, s->host_data.acc, sizeof(s->host_data.acc));
} else {
- pix_count = ATI_HOST_DATA_ACC_BITS;
/* Expand monochrome bits to color pixels */
+ uint32_t byte_pix_order = s->regs.dp_datatype & DP_BYTE_PIX_ORDER;
+ uint32_t fg = make_filler(ctx.bpp, s->regs.dp_src_frgd_clr);
+ uint32_t bg = make_filler(ctx.bpp, s->regs.dp_src_bkgd_clr);
+
+ if (ctx.need_swap) {
+ bswap32s(&fg);
+ bswap32s(&bg);
+ }
idx = 0;
for (int word = 0; word < 4; word++) {
for (int byte = 0; byte < 4; byte++) {
uint8_t byte_val = s->host_data.acc[word] >> (byte * 8);
for (int i = 0; i < 8; i++) {
bool is_fg = byte_val & BIT(byte_pix_order ? i : 7 - i);
- uint32_t color = is_fg ? fg : bg;
- stn_he_p(&pix_buf[idx], bypp, color);
+ stn_he_p(&pix_buf[idx], bypp, is_fg ? fg : bg);
idx += bypp;
}
}
--
2.41.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/5] ati-vga: Also switch mode on HW cursor enable bit change
2026-03-17 23:32 [PATCH v3 0/5] ati-vga fixes BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 1/5] ati-vga: Fix colors when frame buffer endianness does not match host BALATON Zoltan
@ 2026-03-17 23:32 ` BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 3/5] ati-vga: Do not add crtc offset to src and dst data address BALATON Zoltan
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: BALATON Zoltan @ 2026-03-17 23:32 UTC (permalink / raw)
To: qemu-devel
Cc: Gerd Hoffmann, marcandre.lureau, Chad Jablonski,
Philippe Mathieu-Daudé
This does nothing for most drivers but works around issue and fixes
output with the Solaris R128 driver that only sets display parameters
after enabling CRT controller which we would miss otherwise.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Chad Jablonski <chad@jablonski.xyz>
Reviewed-by: Chad Jablonski <chad@jablonski.xyz>
---
hw/display/ati.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/display/ati.c b/hw/display/ati.c
index c165434938..8286f67c1c 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -632,6 +632,7 @@ static void ati_mm_write(void *opaque, hwaddr addr,
ati_reg_write_offs(&s->regs.crtc_gen_cntl,
addr - CRTC_GEN_CNTL, data, size);
if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) {
+ ati_vga_switch_mode(s);
if (s->cursor_guest_mode) {
s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN);
} else {
--
2.41.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 3/5] ati-vga: Do not add crtc offset to src and dst data address
2026-03-17 23:32 [PATCH v3 0/5] ati-vga fixes BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 1/5] ati-vga: Fix colors when frame buffer endianness does not match host BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 2/5] ati-vga: Also switch mode on HW cursor enable bit change BALATON Zoltan
@ 2026-03-17 23:32 ` BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 4/5] ati-vga: Avoid warnings about sign extension BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 5/5] ati-vga: Fix display updates in non-32 bit modes BALATON Zoltan
4 siblings, 0 replies; 6+ messages in thread
From: BALATON Zoltan @ 2026-03-17 23:32 UTC (permalink / raw)
To: qemu-devel
Cc: Gerd Hoffmann, marcandre.lureau, Chad Jablonski,
Philippe Mathieu-Daudé
Drivers seem to program these registers with values that already
include the crtc offset so this is not needed. This fixes blit outside
of vram errors with non-0 crtc offset.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/display/ati_2d.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c
index 0cbbdc33f4..cf2d4a08e2 100644
--- a/hw/display/ati_2d.c
+++ b/hw/display/ati_2d.c
@@ -110,7 +110,6 @@ static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx)
ctx->dst_stride = s->regs.dst_pitch;
ctx->dst_bits = s->vga.vram_ptr + s->regs.dst_offset;
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
- ctx->dst_bits += s->regs.crtc_offset & 0x07ffffff;
ctx->dst_stride *= ctx->bpp;
}
@@ -121,7 +120,6 @@ static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx)
ctx->src_stride = s->regs.src_pitch;
ctx->src_bits = s->vga.vram_ptr + s->regs.src_offset;
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
- ctx->src_bits += s->regs.crtc_offset & 0x07ffffff;
ctx->src_stride *= ctx->bpp;
}
DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",
--
2.41.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 4/5] ati-vga: Avoid warnings about sign extension
2026-03-17 23:32 [PATCH v3 0/5] ati-vga fixes BALATON Zoltan
` (2 preceding siblings ...)
2026-03-17 23:32 ` [PATCH v3 3/5] ati-vga: Do not add crtc offset to src and dst data address BALATON Zoltan
@ 2026-03-17 23:32 ` BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 5/5] ati-vga: Fix display updates in non-32 bit modes BALATON Zoltan
4 siblings, 0 replies; 6+ messages in thread
From: BALATON Zoltan @ 2026-03-17 23:32 UTC (permalink / raw)
To: qemu-devel
Cc: Gerd Hoffmann, marcandre.lureau, Chad Jablonski,
Philippe Mathieu-Daudé
Coverity reports several possible sign extension errors (latest is CID
1645615). These cannot happen because the values are limited when
writing the registers and only 32 bits of the return value matter but
change type of the variable storing the return value to uint32_t to
avoid these warnings. Also change DEFAULT_SC_BOTTOM_RIGHT register
read to match what other similar registers do for consistency.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/display/ati.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/display/ati.c b/hw/display/ati.c
index 8286f67c1c..705e4db6e4 100644
--- a/hw/display/ati.c
+++ b/hw/display/ati.c
@@ -266,7 +266,7 @@ static void ati_vga_vblank_irq(void *opaque)
ati_vga_update_irq(s);
}
-static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs,
+static inline uint32_t ati_reg_read_offs(uint32_t reg, int offs,
unsigned int size)
{
if (offs == 0 && size == 4) {
@@ -279,7 +279,7 @@ static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs,
static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size)
{
ATIVGAState *s = opaque;
- uint64_t val = 0;
+ uint32_t val = 0;
switch (addr) {
case MM_INDEX:
@@ -514,8 +514,8 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size)
val |= s->regs.default_tile << 16;
break;
case DEFAULT_SC_BOTTOM_RIGHT:
- val = (s->regs.default_sc_bottom << 16) |
- s->regs.default_sc_right;
+ val = s->regs.default_sc_right;
+ val |= s->regs.default_sc_bottom << 16;
break;
case SC_TOP:
val = s->regs.sc_top;
--
2.41.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 5/5] ati-vga: Fix display updates in non-32 bit modes
2026-03-17 23:32 [PATCH v3 0/5] ati-vga fixes BALATON Zoltan
` (3 preceding siblings ...)
2026-03-17 23:32 ` [PATCH v3 4/5] ati-vga: Avoid warnings about sign extension BALATON Zoltan
@ 2026-03-17 23:32 ` BALATON Zoltan
4 siblings, 0 replies; 6+ messages in thread
From: BALATON Zoltan @ 2026-03-17 23:32 UTC (permalink / raw)
To: qemu-devel
Cc: Gerd Hoffmann, marcandre.lureau, Chad Jablonski,
Philippe Mathieu-Daudé
The memory_region_set_dirty used to mark changes should use stride
value in vram which is normally only the same as surface_stride in 32
bit modes. This caused missed updates in 8 and 16 bit modes.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/display/ati_2d.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c
index cf2d4a08e2..a1224bbc9f 100644
--- a/hw/display/ati_2d.c
+++ b/hw/display/ati_2d.c
@@ -78,8 +78,8 @@ static void ati_set_dirty(VGACommonState *vga, const ATI2DCtx *ctx)
vga->vbe_regs[VBE_DISPI_INDEX_YRES] * vga->vbe_line_offset) {
memory_region_set_dirty(&vga->vram,
vga->vbe_start_addr + ctx->dst_offset +
- ctx->dst.y * surface_stride(ds),
- ctx->dst.height * surface_stride(ds));
+ ctx->dst.y * ctx->dst_stride,
+ ctx->dst.height * ctx->dst_stride);
}
}
--
2.41.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2026-03-17 23:32 [PATCH v3 0/5] ati-vga fixes BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 1/5] ati-vga: Fix colors when frame buffer endianness does not match host BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 2/5] ati-vga: Also switch mode on HW cursor enable bit change BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 3/5] ati-vga: Do not add crtc offset to src and dst data address BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 4/5] ati-vga: Avoid warnings about sign extension BALATON Zoltan
2026-03-17 23:32 ` [PATCH v3 5/5] ati-vga: Fix display updates in non-32 bit modes BALATON Zoltan
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