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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from SJ0PR11MB4798.namprd11.prod.outlook.com (2603:10b6:a03:2d5::12) by PH7PR11MB8124.namprd11.prod.outlook.com (2603:10b6:510:237::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9228.10; Wed, 15 Oct 2025 12:31:49 +0000 Received: from SJ0PR11MB4798.namprd11.prod.outlook.com ([fe80::d946:6abf:6e7e:fd1e]) by SJ0PR11MB4798.namprd11.prod.outlook.com ([fe80::d946:6abf:6e7e:fd1e%7]) with mapi id 15.20.9228.010; Wed, 15 Oct 2025 12:31:49 +0000 Message-ID: <8a18e210-9ea4-45a3-8d67-69cb1d167b69@intel.com> Date: Wed, 15 Oct 2025 20:38:36 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] intel_iommu: Handle PASID cache invalidation To: Zhenzhong Duan , CC: , , , References: <20251015102003.279239-1-zhenzhong.duan@intel.com> <20251015102003.279239-2-zhenzhong.duan@intel.com> Content-Language: en-US From: Yi Liu In-Reply-To: <20251015102003.279239-2-zhenzhong.duan@intel.com> Content-Type: text/plain; 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envelope-from=yi.l.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2025/10/15 18:20, Zhenzhong Duan wrote: > Adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the pasid > entry and track PASID usage and future PASID tagged DMA address translation > support in vIOMMU. > > When guest triggers pasid cache invalidation, QEMU will capture it and > update or invalidate pasid cache. > > vIOMMU emulator could figure out the reason by fetching latest guest pasid > entry in memory and compare it with cached PASID entry if it's valid. > > Signed-off-by: Yi Liu > Signed-off-by: Zhenzhong Duan > --- > hw/i386/intel_iommu_internal.h | 19 ++++- > include/hw/i386/intel_iommu.h | 6 ++ > hw/i386/intel_iommu.c | 150 ++++++++++++++++++++++++++++++--- > hw/i386/trace-events | 3 + > 4 files changed, 165 insertions(+), 13 deletions(-) > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index 0f6a1237e4..80193ff28b 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -316,6 +316,8 @@ typedef enum VTDFaultReason { > * request while disabled */ > VTD_FR_IR_SID_ERR = 0x26, /* Invalid Source-ID */ > > + VTD_FR_RTADDR_INV_TTM = 0x31, /* Invalid TTM in RTADDR */ > + > VTD_FR_SM_PRE_ABS = 0x47, /* SCT.8 : PRE bit in a present SM CE is 0 */ > > /* PASID directory entry access failure */ > @@ -517,6 +519,15 @@ typedef union VTDPRDesc VTDPRDesc; > #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL > #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL > > +/* PASID-cache Invalidate Descriptor (pc_inv_dsc) fields */ > +#define VTD_INV_DESC_PASIDC_G(x) extract64((x)->val[0], 4, 2) > +#define VTD_INV_DESC_PASIDC_G_DSI 0 > +#define VTD_INV_DESC_PASIDC_G_PASID_SI 1 > +#define VTD_INV_DESC_PASIDC_G_GLOBAL 3 > +#define VTD_INV_DESC_PASIDC_DID(x) extract64((x)->val[0], 16, 16) > +#define VTD_INV_DESC_PASIDC_PASID(x) extract64((x)->val[0], 32, 20) > +#define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000f1c0ULL > + > /* Page Request Descriptor */ > /* For the low 64-bit of 128-bit */ > #define VTD_PRD_TYPE (1ULL) > @@ -603,6 +614,12 @@ typedef struct VTDRootEntry VTDRootEntry; > #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL > #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL > > +typedef struct VTDPASIDCacheInfo { > + uint8_t type; > + uint16_t did; > + uint32_t pasid; > +} VTDPASIDCacheInfo; > + > /* PASID Table Related Definitions */ > #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) > #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) > @@ -624,7 +641,7 @@ typedef struct VTDRootEntry VTDRootEntry; > #define VTD_SM_PASID_ENTRY_PT (4ULL << 6) > > #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-width */ > -#define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK) > +#define VTD_SM_PASID_ENTRY_DID(x) extract64((x)->val[1], 0, 16) I think this can be done in a separate patch. > > #define VTD_SM_PASID_ENTRY_FLPM 3ULL > #define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) > diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h > index 47730ac3c7..6e68734b3c 100644 > --- a/include/hw/i386/intel_iommu.h > +++ b/include/hw/i386/intel_iommu.h > @@ -95,6 +95,11 @@ struct VTDPASIDEntry { > uint64_t val[8]; > }; > > +typedef struct VTDPASIDCacheEntry { > + struct VTDPASIDEntry pasid_entry; > + bool valid; > +} VTDPASIDCacheEntry; > + > struct VTDAddressSpace { > PCIBus *bus; > uint8_t devfn; > @@ -107,6 +112,7 @@ struct VTDAddressSpace { > MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */ > IntelIOMMUState *iommu_state; > VTDContextCacheEntry context_cache_entry; > + VTDPASIDCacheEntry pasid_cache_entry; > QLIST_ENTRY(VTDAddressSpace) next; > /* Superset of notifier flags that this address space has */ > IOMMUNotifierFlag notifier_flags; > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 6a168d5107..66f45f89cb 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -1607,7 +1607,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, > > if (s->root_scalable) { > vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); > - return VTD_SM_PASID_ENTRY_DID(pe.val[1]); > + return VTD_SM_PASID_ENTRY_DID(&pe); > } > > return VTD_CONTEXT_ENTRY_DID(ce->hi); > @@ -3051,6 +3051,135 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *s, > return true; > } > > +static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as, > + VTDPASIDEntry *pe) > +{ > + IntelIOMMUState *s = vtd_as->iommu_state; > + VTDContextEntry ce; > + int ret; > + > + if (!s->root_scalable) { > + return -VTD_FR_RTADDR_INV_TTM; > + } > + > + ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->devfn, > + &ce); > + if (ret) { > + return ret; > + } > + > + return vtd_ce_get_rid2pasid_entry(s, &ce, pe, vtd_as->pasid); > +} > + > +/* > + * Update or invalidate pasid cache based on the value in memory. s/the value in memory./the pasid entry in guest memory. > + */ > +static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value, > + gpointer user_data) > +{ > + VTDPASIDCacheInfo *pc_info = user_data; > + VTDAddressSpace *vtd_as = value; > + VTDPASIDCacheEntry *pc_entry = &vtd_as->pasid_cache_entry; > + VTDPASIDEntry pe; > + uint16_t did; > + > + if (vtd_dev_get_pe_from_pasid(vtd_as, &pe)) { > + /* > + * No valid pasid entry in guest memory. e.g. pasid entry was modified > + * to be either all-zero or non-present. Either case means existing > + * pasid cache should be invalidated. > + */ > + pc_entry->valid = false; > + return; > + } > + > + /* > + * VTD_INV_DESC_PASIDC_G_DSI and VTD_INV_DESC_PASIDC_G_PASID_SI require > + * DID check. If DID doesn't match the value in cache or memory, then > + * it's not a pasid entry we want to invalidate. > + */ > + switch (pc_info->type) { > + case VTD_INV_DESC_PASIDC_G_PASID_SI: > + if (pc_info->pasid != vtd_as->pasid) { > + return; > + } > + /* Fall through */ > + case VTD_INV_DESC_PASIDC_G_DSI: > + if (pc_entry->valid) { > + did = VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); > + if (pc_info->did == did) { > + break; > + } > + } > + did = VTD_SM_PASID_ENTRY_DID(&pe); > + if (pc_info->did == did) { > + break; > + } hmmm. how about below? /* * For newly set pasid entry, iommu driver is supposed to * invalidate pasid cache with the did configed in pasid entry * when caching-mode is reported. Oherwise qemu vIOMMU just skip * it. */ if pc_entry->valid) { did = VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); } else { did = VTD_SM_PASID_ENTRY_DID(&pe); } if (pc_info->did != did) { return; } Regards, Yi Liu > + return; > + } > + > + pc_entry->pasid_entry = pe; > + pc_entry->valid = true; > +} > + > +static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info) > +{ > + if (!s->root_scalable || !s->dmar_enabled) { > + return; > + } > + > + vtd_iommu_lock(s); > + g_hash_table_foreach(s->vtd_address_spaces, vtd_pasid_cache_sync_locked, > + pc_info); > + vtd_iommu_unlock(s); > +} > + > +static bool vtd_process_pasid_desc(IntelIOMMUState *s, > + VTDInvDesc *inv_desc) > +{ > + uint16_t did; > + uint32_t pasid; > + VTDPASIDCacheInfo pc_info = {}; > + uint64_t mask[4] = {VTD_INV_DESC_PASIDC_RSVD_VAL0, VTD_INV_DESC_ALL_ONE, > + VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE}; > + > + if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, true, > + __func__, "pasid cache inv")) { > + return false; > + } > + > + did = VTD_INV_DESC_PASIDC_DID(inv_desc); > + pasid = VTD_INV_DESC_PASIDC_PASID(inv_desc); > + pc_info.type = VTD_INV_DESC_PASIDC_G(inv_desc); > + > + switch (pc_info.type) { > + case VTD_INV_DESC_PASIDC_G_DSI: > + trace_vtd_inv_desc_pasid_cache_dsi(did); > + pc_info.did = did; > + break; > + > + case VTD_INV_DESC_PASIDC_G_PASID_SI: > + /* PASID selective implies a DID selective */ > + trace_vtd_inv_desc_pasid_cache_psi(did, pasid); > + pc_info.did = did; > + pc_info.pasid = pasid ?: PCI_NO_PASID; > + break; > + > + case VTD_INV_DESC_PASIDC_G_GLOBAL: > + trace_vtd_inv_desc_pasid_cache_gsi(); > + break; > + > + default: > + error_report_once("invalid granularity field in PASID-cache invalidate " > + "descriptor, hi: 0x%"PRIx64" lo: 0x%" PRIx64, > + inv_desc->val[1], inv_desc->val[0]); > + return false; > + } > + > + vtd_pasid_cache_sync(s, &pc_info); > + return true; > +} > + > static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, > VTDInvDesc *inv_desc) > { > @@ -3266,6 +3395,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) > } > break; > > + case VTD_INV_DESC_PC: > + trace_vtd_inv_desc("pasid-cache", inv_desc.val[1], inv_desc.val[0]); > + if (!vtd_process_pasid_desc(s, &inv_desc)) { > + return false; > + } > + break; > + > case VTD_INV_DESC_PIOTLB: > trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); > if (!vtd_process_piotlb_desc(s, &inv_desc)) { > @@ -3308,16 +3444,6 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) > } > break; > > - /* > - * TODO: the entity of below two cases will be implemented in future series. > - * To make guest (which integrates scalable mode support patch set in > - * iommu driver) work, just return true is enough so far. > - */ > - case VTD_INV_DESC_PC: > - if (s->scalable_mode) { > - break; > - } > - /* fallthrough */ > default: > error_report_once("%s: invalid inv desc: hi=%"PRIx64", lo=%"PRIx64 > " (unknown type)", __func__, inv_desc.hi, > @@ -5005,7 +5131,7 @@ static int vtd_pri_perform_implicit_invalidation(VTDAddressSpace *vtd_as, > return -EINVAL; > } > pgtt = VTD_PE_GET_TYPE(&pe); > - domain_id = VTD_SM_PASID_ENTRY_DID(pe.val[1]); > + domain_id = VTD_SM_PASID_ENTRY_DID(&pe); > ret = 0; > switch (pgtt) { > case VTD_SM_PASID_ENTRY_FLT: > diff --git a/hw/i386/trace-events b/hw/i386/trace-events > index ac9e1a10aa..298addb24d 100644 > --- a/hw/i386/trace-events > +++ b/hw/i386/trace-events > @@ -24,6 +24,9 @@ vtd_inv_qi_head(uint16_t head) "read head %d" > vtd_inv_qi_tail(uint16_t head) "write tail %d" > vtd_inv_qi_fetch(void) "" > vtd_context_cache_reset(void) "" > +vtd_inv_desc_pasid_cache_gsi(void) "" > +vtd_inv_desc_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation domain 0x%"PRIx16 > +vtd_inv_desc_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 > vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" > vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8" devfn %"PRIu8" not present" > vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t domain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" domain 0x%"PRIx16