Re: [PULL 0/7] target/rx patch queue

[Richard Henderson <richard.henderson@linaro.org>]

On 4/21/22 10:31, Richard Henderson wrote:
> The following changes since commit 401d46789410e88e9e90d76a11f46e8e9f358d55:
> 
>    Merge tag 'pull-target-arm-20220421' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-21 08:04:43 -0700)
> 
> are available in the Git repository at:
> 
>    https://gitlab.com/rth7680/qemu.git tags/pull-rx-20220421
> 
> for you to fetch changes up to 724eaecec6d22cf3842f896684bdc5b79492f093:
> 
>    target/rx: update PC correctly in wait instruction (2022-04-21 10:09:12 -0700)
> 
> ----------------------------------------------------------------
> Fix usp/isp swapping upon clrpsw/setpsw.
> Fix psw.i/pc upon wait.
> Align dtb in ram.

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.


r~



> 
> ----------------------------------------------------------------
> Richard Henderson (4):
>        target/rx: Put tb_flags into DisasContext
>        target/rx: Store PSW.U in tb->flags
>        target/rx: Move DISAS_UPDATE check for write to PSW
>        target/rx: Swap stack pointers on clrpsw/setpsw instruction
> 
> Tomoaki Kawada (2):
>        target/rx: set PSW.I when executing wait instruction
>        target/rx: update PC correctly in wait instruction
> 
> Yoshinori Sato (1):
>        hw/rx: rx-gdbsim DTB load address aligned of 16byte.
> 
>   target/rx/cpu.h       |  1 +
>   hw/rx/rx-gdbsim.c     |  2 +-
>   target/rx/op_helper.c |  1 +
>   target/rx/translate.c | 69 +++++++++++++++++++++++++++------------------------
>   4 files changed, 40 insertions(+), 33 deletions(-)