From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:44937) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ggx1K-0002IE-Dm for qemu-devel@nongnu.org; Tue, 08 Jan 2019 14:26:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ggx1H-0004Cy-Bw for qemu-devel@nongnu.org; Tue, 08 Jan 2019 14:26:37 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:46624) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ggx1G-0003sJ-GX for qemu-devel@nongnu.org; Tue, 08 Jan 2019 14:26:35 -0500 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id x08JQL1N103192 for ; Tue, 8 Jan 2019 14:26:24 -0500 Received: from e33.co.us.ibm.com (e33.co.us.ibm.com [32.97.110.151]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pvx77v8tq-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 08 Jan 2019 14:26:23 -0500 Received: from localhost by e33.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 8 Jan 2019 19:25:16 -0000 References: <20190108084039.9254-1-marcandre.lureau@redhat.com> <20190108084039.9254-7-marcandre.lureau@redhat.com> From: Stefan Berger Date: Tue, 8 Jan 2019 14:25:05 -0500 MIME-Version: 1.0 In-Reply-To: <20190108084039.9254-7-marcandre.lureau@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-MW Message-Id: <8a2f71b4-fe55-2bf7-20db-85b17335b0de@linux.ibm.com> Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v14 6/6] tpm: clear RAM when "memory overwrite" requested List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , qemu-devel@nongnu.org Cc: Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , stefanb@linux.vnet.ibm.com, f4bug@amsat.org, "Michael S. Tsirkin" , Igor Mammedov , Richard Henderson On 1/8/19 3:40 AM, Marc-Andr=C3=A9 Lureau wrote: > Note: the "Platform Reset Attack Mitigation" specification isn't > explicit about NVDIMM, since they could have different usages. It uses > the term "system memory" generally (and also "volatile memory RAM" in > its introduction). For initial support, I propose to consider > non-volatile memory as not being subject to the memory clear. There is > an on-going discussion in the TCG "pcclientwg" working group for > future revisions. > > CPU cache clearing is done unconditionally in edk2 since commit > d20ae95a13e851 (edk2-stable201811). I just tried to test the series(from level of virt-manager).=20 Unfortunately this patch here seems to break QEMU... > > Signed-off-by: Marc-Andr=C3=A9 Lureau > --- > hw/tpm/tpm_ppi.h | 10 ++++++++++ > hw/tpm/tpm_crb.c | 1 + > hw/tpm/tpm_ppi.c | 22 ++++++++++++++++++++++ > hw/tpm/tpm_tis.c | 1 + > hw/tpm/trace-events | 3 +++ > 5 files changed, 37 insertions(+) > > diff --git a/hw/tpm/tpm_ppi.h b/hw/tpm/tpm_ppi.h > index c5e555fe2c..d33ef27de6 100644 > --- a/hw/tpm/tpm_ppi.h > +++ b/hw/tpm/tpm_ppi.h > @@ -33,4 +33,14 @@ typedef struct TPMPPI { > void tpm_ppi_init(TPMPPI *tpmppi, struct MemoryRegion *m, > hwaddr addr, Object *obj); > =20 > +/** > + * tpm_ppi_reset: > + * @tpmppi: a TPMPPI > + * > + * Function to call on machine reset. It will check if the "Memory > + * overwrite" variable is set, and perform a memory clear on volatile > + * memory if requested. > + **/ > +void tpm_ppi_reset(TPMPPI *tpmppi); > + > #endif /* TPM_TPM_PPI_H */ > diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c > index 012ec686d4..663469bd20 100644 > --- a/hw/tpm/tpm_crb.c > +++ b/hw/tpm/tpm_crb.c > @@ -233,6 +233,7 @@ static void tpm_crb_reset(void *dev) > { > CRBState *s =3D CRB(dev); > =20 > + tpm_ppi_reset(&s->ppi); > tpm_backend_reset(s->tpmbe); > =20 > memset(s->regs, 0, sizeof(s->regs)); > diff --git a/hw/tpm/tpm_ppi.c b/hw/tpm/tpm_ppi.c > index cf17779c20..cd8205f212 100644 > --- a/hw/tpm/tpm_ppi.c > +++ b/hw/tpm/tpm_ppi.c > @@ -16,8 +16,30 @@ > #include "qapi/error.h" > #include "cpu.h" > #include "sysemu/memory_mapping.h" > +#include "sysemu/reset.h" > #include "migration/vmstate.h" > #include "tpm_ppi.h" > +#include "trace.h" > + > +void tpm_ppi_reset(TPMPPI *tpmppi) > +{ > + if (tpmppi->buf[0x15a /* movv, docs/specs/tpm.txt */] & 0x1) { this has to be: if (tpmppi->buf && tpmppi->buf[0x15a ...]) > + GuestPhysBlockList guest_phys_blocks; > + GuestPhysBlock *block; > + > + guest_phys_blocks_init(&guest_phys_blocks); > + guest_phys_blocks_append(&guest_phys_blocks); > + QTAILQ_FOREACH(block, &guest_phys_blocks.head, next) { > + trace_tpm_ppi_memset(block->host_addr, > + block->target_end - block->target_sta= rt); > + memset(block->host_addr, 0, > + block->target_end - block->target_start); > + memory_region_set_dirty(block->mr, 0, > + block->target_end - block->target_= start); > + } > + guest_phys_blocks_free(&guest_phys_blocks); > + } > +} > =20 > void tpm_ppi_init(TPMPPI *tpmppi, struct MemoryRegion *m, > hwaddr addr, Object *obj) > diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c > index 02d9d5c911..6a5511e042 100644 > --- a/hw/tpm/tpm_tis.c > +++ b/hw/tpm/tpm_tis.c > @@ -872,6 +872,7 @@ static void tpm_tis_reset(DeviceState *dev) > s->be_buffer_size =3D MIN(tpm_backend_get_buffer_size(s->be_drive= r), > TPM_TIS_BUFFER_MAX); > =20 > + tpm_ppi_reset(&s->ppi); > tpm_backend_reset(s->be_driver); > =20 > s->active_locty =3D TPM_TIS_NO_LOCALITY; > diff --git a/hw/tpm/trace-events b/hw/tpm/trace-events > index 25bee0cecf..920d32ad55 100644 > --- a/hw/tpm/trace-events > +++ b/hw/tpm/trace-events > @@ -51,3 +51,6 @@ tpm_tis_mmio_write_init_abort(void) "Initiating abort= " > tpm_tis_mmio_write_lowering_irq(void) "Lowering IRQ" > tpm_tis_mmio_write_data2send(uint32_t value, unsigned size) "Data to = send to TPM: 0x%08x (size=3D%d)" > tpm_tis_pre_save(uint8_t locty, uint32_t rw_offset) "locty: %d, rw_of= fset =3D %u" > + > +# hw/tpm/tpm_ppi.c > +tpm_ppi_memset(uint8_t *ptr, size_t size) "memset: %p %zu"