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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Song Gao <gaosong@loongson.cn>, qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, c@jia.je, maobibo@loongson.cn,
	yangxiaojuan@loongson.cn, yijun@loongson.cn,
	shenjinyang@loongson.cn
Subject: Re: [PATCH v4 09/15] target/loongarch: Add LoongArch32 cpu la132
Date: Tue, 22 Aug 2023 08:56:07 +0200	[thread overview]
Message-ID: <8a37fa1d-e967-30be-1cb0-bcb0c8196792@linaro.org> (raw)
In-Reply-To: <20230822032724.1353391-10-gaosong@loongson.cn>

On 22/8/23 05:27, Song Gao wrote:
> From: Jiajie Chen <c@jia.je>
> 
> Add LoongArch32 cpu la132.
> 
> Due to lack of public documentation of la132, it is currently a
> synthetic LoongArch32 cpu model. Details need to be added in the future.
> 
> Signed-off-by: Jiajie Chen <c@jia.je>
> Signed-off-by: Song Gao <gaosong@loongson.cn>
> ---
>   target/loongarch/cpu.c | 30 ++++++++++++++++++++++++++++++

Thanks for splitting the hw/ patch out, ...

>   1 file changed, 30 insertions(+)
> 
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 67eb6c3135..d3c3e0d8a1 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -440,6 +440,35 @@ static void loongarch_la464_initfn(Object *obj)
>       env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
>   }
>   
> +static void loongarch_la132_initfn(Object *obj)
> +{
> +    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> +    CPULoongArchState *env = &cpu->env;
> +
> +    int i;
> +
> +    for (i = 0; i < 21; i++) {
> +        env->cpucfg[i] = 0x0;
> +    }
> +
> +    cpu->dtb_compatible = "loongarch,Loongson-1C103";
> +    env->cpucfg[0] = 0x148042;  /* PRID */

... and filling the PRid register.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>



  parent reply	other threads:[~2023-08-22  6:56 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-22  3:27 [PATCH v4 00/15] Add some checks before translating instructions Song Gao
2023-08-22  3:27 ` [PATCH v4 01/15] target/loongarch: Support LoongArch32 TLB entry Song Gao
2023-08-22  3:27 ` [PATCH v4 02/15] target/loongarch: Support LoongArch32 DMW Song Gao
2023-08-22  3:27 ` [PATCH v4 03/15] target/loongarch: Support LoongArch32 VPPN Song Gao
2023-08-22  3:27 ` [PATCH v4 04/15] target/loongarch: Add LA64 & VA32 to DisasContext Song Gao
2023-08-22  3:27 ` [PATCH v4 05/15] target/loongarch: Truncate high 32 bits of address in VA32 mode Song Gao
2023-08-22  7:05   ` Philippe Mathieu-Daudé
2023-08-22  3:27 ` [PATCH v4 06/15] target/loongarch: Sign extend results " Song Gao
2023-08-22  7:05   ` Philippe Mathieu-Daudé
2023-08-22  3:27 ` [PATCH v4 07/15] target/loongarch: Add a check parameter to the TRANS macro Song Gao
2023-08-22  3:27 ` [PATCH v4 08/15] target/loongarch: Add avail_64 to check la64-only instructions Song Gao
2023-08-22  3:27 ` [PATCH v4 09/15] target/loongarch: Add LoongArch32 cpu la132 Song Gao
2023-08-22  4:29   ` Richard Henderson
2023-08-22  6:56   ` Philippe Mathieu-Daudé [this message]
2023-08-22  3:27 ` [PATCH v4 10/15] hw/loongarch: Remove restriction of la464 cores in the virt machine Song Gao
2023-08-22  4:29   ` Richard Henderson
2023-08-22  6:56   ` Philippe Mathieu-Daudé
2023-08-22  3:27 ` [PATCH v4 11/15] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions Song Gao
2023-08-22  3:27 ` [PATCH v4 12/15] target/loongarch: Add avail_LSPW to check LSPW instructions Song Gao
2023-08-22  3:27 ` [PATCH v4 13/15] target/loongarch: Add avail_LAM to check atomic instructions Song Gao
2023-08-22  3:27 ` [PATCH v4 14/15] target/loongarch: Add avail_LSX to check LSX instructions Song Gao
2023-08-22  3:27 ` [PATCH v4 15/15] target/loongarch: Add avail_IOCSR to check iocsr instructions Song Gao

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