From: Richard Henderson <richard.henderson@linaro.org>
To: "Christoph Muellner" <christoph.muellner@vrull.eu>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Heiko Stübner" <heiko.stuebner@vrull.eu>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Nelson Chu" <nelson@rivosinc.com>,
"Kito Cheng" <kito.cheng@sifive.com>,
"Cooper Qu" <cooper.qu@linux.alibaba.com>,
"Lifang Xia" <lifang_xia@linux.alibaba.com>,
"Yunhai Shang" <yunhai@linux.alibaba.com>,
"Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH v3 02/14] RISC-V: Adding XTheadSync ISA extension
Date: Tue, 24 Jan 2023 10:21:52 -1000 [thread overview]
Message-ID: <8a81e02c-5bb7-a82b-be16-e93362169a44@linaro.org> (raw)
In-Reply-To: <20230124195945.181842-3-christoph.muellner@vrull.eu>
On 1/24/23 09:59, Christoph Muellner wrote:
> +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
> +{
> + (void) a;
> + REQUIRE_XTHEADSYNC(ctx);
> +
> +#ifndef CONFIG_USER_ONLY
> + REQUIRE_PRIV_MS(ctx);
> + decode_save_opc(ctx);
> + gen_helper_tlb_flush_all(cpu_env);
Why are you using decode_save_opc() when helper_tlb_flush_all() cannot raise an exception?
r~
next prev parent reply other threads:[~2023-01-24 20:22 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-24 19:59 [PATCH v3 00/14] Add support for the T-Head vendor extensions Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 01/14] RISC-V: Adding XTheadCmo ISA extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 02/14] RISC-V: Adding XTheadSync " Christoph Muellner
2023-01-24 20:21 ` Richard Henderson [this message]
2023-01-30 14:05 ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 03/14] RISC-V: Adding XTheadBa " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 04/14] RISC-V: Adding XTheadBb " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 05/14] RISC-V: Adding XTheadBs " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 06/14] RISC-V: Adding XTheadCondMov " Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension Christoph Muellner
2023-01-24 20:44 ` Richard Henderson
2023-01-30 2:03 ` LIU Zhiwei
2023-01-30 5:43 ` Richard Henderson
2023-01-30 8:41 ` LIU Zhiwei
2023-01-30 19:03 ` Richard Henderson
2023-01-31 2:34 ` LIU Zhiwei
2023-01-31 18:01 ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension Christoph Muellner
2023-01-24 21:21 ` Richard Henderson
2023-01-30 9:04 ` LIU Zhiwei
2023-01-31 18:01 ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 10/14] RISC-V: Adding T-Head FMemIdx extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 12/14] RISC-V: Add initial support for T-Head C906 Christoph Muellner
2023-01-24 21:26 ` Richard Henderson
2023-01-30 9:06 ` LIU Zhiwei
2023-01-31 18:01 ` Christoph Müllner
2023-01-24 19:59 ` [PATCH v3 13/14] RISC-V: Adding XTheadFmv ISA extension Christoph Muellner
2023-01-24 19:59 ` [PATCH v3 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Christoph Muellner
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