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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9b5939sm11670228f8f.60.2025.03.24.09.39.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Mar 2025 09:39:36 -0700 (PDT) Message-ID: <8a81f554-dcb5-4086-88cc-d1c099a05761@linaro.org> Date: Mon, 24 Mar 2025 17:39:35 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH-for-10.1 4/4] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field To: BALATON Zoltan , Richard Henderson Cc: qemu-devel@nongnu.org, =?UTF-8?Q?Alex_Benn=C3=A9e?= , qemu-ppc , Anton Johansson , Pierrick Bouvier , Paolo Bonzini , Mark Cave-Ayland , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= References: <20250321155925.96626-1-philmd@linaro.org> <20250321155925.96626-5-philmd@linaro.org> <8cc6f6a4-b868-4dc8-bc14-25b438ad62a5@linaro.org> <5bd8498c-b5ff-4fb1-94d7-a2efa2f20fd9@linaro.org> <4e569101-042f-e0a6-23be-e4fbeb79c3b7@eik.bme.hu> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <4e569101-042f-e0a6-23be-e4fbeb79c3b7@eik.bme.hu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 23/3/25 23:49, BALATON Zoltan wrote: > On Sun, 23 Mar 2025, Richard Henderson wrote: >> On 3/23/25 15:13, BALATON Zoltan wrote: >>> On Sun, 23 Mar 2025, Philippe Mathieu-Daudé wrote: >>>> On 23/3/25 20:07, Richard Henderson wrote: >>>>>> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c >>>>>> index 28fbbb8d3c1..ed79cc1a6b7 100644 >>>>>> --- a/target/ppc/cpu_init.c >>>>>> +++ b/target/ppc/cpu_init.c >>>>>> @@ -7490,6 +7490,7 @@ static const TCGCPUOps ppc_tcg_ops = { >>>>>>     .translate_code = ppc_translate_code, >>>>>>     .restore_state_to_opc = ppc_restore_state_to_opc, >>>>>> +  .mttcg_supported = TARGET_LONG_BITS == 64, >>>>>>     .guest_default_memory_order = 0, >>>>> >>>>> Similarly.  I'd be surprised if ppc32 can't use mttcg, really. >>>> >>>> Per Cédric on IRC our ppc32 implementations are single core, >>>> so never tested for mttcg. >>> >>> We're just trying to implement more CPUs for G4 mac99 and tested it >>> with -smp 2 and it seems to generally work but we need to implement >>> more of the Mac hardware for this but we could already run Mac OS X >>> with two CPUs and mttcg and Linux too if we add a delay on boot when >>> second CPU is started (it may need implementing timebase control as >>> done on the G4 Mac to avoid that but if it gets past that it seems to >>> work). So please leave this enabled. Not tested does not mean it does >>> not work so only disable if there's a known problem. >> >> MTTCG is not enabled for qemu-system-ppc right now. > > I could use -smp 2 with qemu-system-ppc after this: > https://lists.nongnu.org/archive/html/qemu-ppc/2025-02/msg00377.html > It complains about not tested for the board but works nevertheless. I > don't remember if I've enabled mttcg or not so maybe it only ran with > single thread which was enough for testing but others did test mttcg: > https://lists.nongnu.org/archive/html/qemu-ppc/2025-02/msg00455.html > although could be that with qemu-system-ppc64 which also includes 32 bit > machines. But then it should work the same with qemu-system-ppc so it > could be enabled there as well. > >> Phil's patch does not current change behaviour. > > Then what does the line do at all? In any case we may want to enable > mttcg in qemu-system-ppc in the future so maybe there's no need to > restrict it here. In the future you can enable it posting this patch: -- >8 -- diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c @@ -7492,6 +7492,7 @@ static const TCGCPUOps ppc_tcg_ops = { - .mttcg_supported = TARGET_LONG_BITS == 64, + .mttcg_supported = true, --- which is equivalent of today's: -- >8 -- diff --git a/configs/targets/ppc-softmmu.mak b/configs/targets/ppc-softmmu.mak @@ -5 +5,2 @@ TARGET_XML_FILES= gdb-xml/power-core.xml gdb-xml/power-fpu.xml gdb-xml/power-alt TARGET_LONG_BITS=32 +TARGET_SUPPORTS_MTTCG=y --- I'll let you write the commit description. Regards, Phil.