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Mon, 23 Aug 2021 10:36:37 -0700 (PDT) Received: from [192.168.1.11] ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id o10sm18256333pgp.68.2021.08.23.10.36.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Aug 2021 10:36:37 -0700 (PDT) Subject: Re: [PATCH v3 14/15] target/riscv: rewrite slli.uw implementation to mirror formal spec To: Philipp Tomsich , qemu-devel@nongnu.org References: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> <20210823164038.2195113-15-philipp.tomsich@vrull.eu> From: Richard Henderson Message-ID: <8aba9c79-8af4-c755-f982-52edb36f4397@linaro.org> Date: Mon, 23 Aug 2021 10:36:35 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210823164038.2195113-15-philipp.tomsich@vrull.eu> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.023, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/23/21 9:40 AM, Philipp Tomsich wrote: > The slli.uw instruction is defined as > X(rd) = (EXTZ(X(rs)[31..0]) << shamt); > > This rewrites its implementation to directly match this, allowing > for the small optimisation of not emitting the zero-extension if > the immediate shift is greater than 32. > > Signed-off-by: Philipp Tomsich > --- > > (no changes since v1) > > target/riscv/insn_trans/trans_rvb.c.inc | 15 ++++++--------- > 1 file changed, 6 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index b134abd263..3419dcf1bb 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -308,17 +308,14 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) > return false; > } > > - TCGv source1 = tcg_temp_new(); > - gen_get_gpr(source1, a->rs1); > - > + TCGv source = tcg_temp_new(); > + gen_get_gpr(source, a->rs1); > if (a->shamt < 32) { > - tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32); > - } else { > - tcg_gen_shli_tl(source1, source1, a->shamt); > + tcg_gen_ext32u_tl(source, source); > } Why? You're replacing one operation with two, when the host supports this deposit operation. r~ > - > - gen_set_gpr(a->rd, source1); > - tcg_temp_free(source1); > + tcg_gen_shli_tl(source, source, a->shamt); > + gen_set_gpr(a->rd, source); > + tcg_temp_free(source); > return true; > } > >