From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>,
qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v7 02/14] disas: nanoMIPS: Add graphical description of pool organization
Date: Tue, 5 Mar 2019 13:04:04 +0100 [thread overview]
Message-ID: <8acd73e1-219f-b5f7-e001-6f6dd086171d@redhat.com> (raw)
In-Reply-To: <1551733750-4902-3-git-send-email-aleksandar.markovic@rt-rk.com>
On 3/4/19 10:08 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Add graphical description of nanoMIPS instruction pool organization.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> disas/nanomips.cpp | 102 +++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 102 insertions(+)
>
> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
> index 10f6d96..9b44208 100644
> --- a/disas/nanomips.cpp
> +++ b/disas/nanomips.cpp
> @@ -16592,6 +16592,108 @@ std::string NMD::YIELD(uint64 instruction)
>
>
>
> +/*
> + * nanoMIPS instruction pool organization
> + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> + *
> + *
> + * ┌─ P.ADDIU ─── P.RI ─── P.SYSCALL
> + * │
> + * │ ┌─ P.TRAP
> + * │ │
> + * │ ┌─ _POOL32A0_0 ─┼─ P.CMOVE
> + * │ │ │
> + * │ │ └─ P.SLTU
> + * │ ┌─ _POOL32A0 ─┤
> + * │ │ │
> + * │ │ │
> + * │ │ └─ _POOL32A0_1 ─── CRC32
> + * │ │
> + * ├─ P32A ─┤
> + * │ │ ┌─ PP.LSX
> + * │ │ ┌─ P.LSX ─────┤
> + * │ │ │ └─ PP.LSXS
> + * │ └─ _POOL32A7 ─┤
> + * │ │ ┌─ POOL32Axf_4
> + * │ └─ POOL32Axf ─┤
> + * │ └─ POOL32Axf_5
> + * │
> + * ├─ PBAL
> + * │
> + * ├─ P.GP.W ┌─ PP.LSX
> + * ┌─ P32 ─┤ │
> + * │ ├─ P.GP.BH ─┴─ PP.LSXS
> + * │ │
> + * │ ├─ P.J ─────── PP.BALRSC
> + * │ │
> + * │ ├─ P48I
> + * │ │ ┌─ P.SR
> + * │ │ │
> + * │ │ ├─ P.SHIFT
> + * │ │ │
> + * │ ├─ P.U12 ───┼─ P.ROTX
> + * │ │ │
> + * │ │ ├─ P.INS
> + * │ │ │
> + * │ │ └─ P.EXT
> + * │ │
> + * │ ├─ P.LS.U12 ── P.PREF.U12
> + * │ │
> + * │ ├─ P.BR1 ───── P.BR3A
> + * │ │
> + * │ │ ┌─ P.LS.S0 ─── P16.SYSCALL
> + * │ │ │
> + * │ │ │ ┌─ P.LL
> + * │ │ ├─ P.LS.S1 ─┤
> + * │ │ │ └─ P.SC
> + * │ │ │
> + * │ │ │ ┌─ P.PREFE
> + * MAJOR ─┤ ├─ P.LS.S9 ─┤ │
> + * │ │ ├─ P.LS.E0 ─┼─ P.LLE
> + * │ │ │ │
> + * │ │ │ └─ P.SCE
> + * │ │ │
> + * │ │ ├─ P.LS.WM
> + * │ │ │
> + * │ │ └─ P.LS.UAWM
> + * │ │
> + * │ │
> + * │ ├─ P.BR2
> + * │ │
> + * │ ├─ P.BRI
> + * │ │
> + * │ └─ P.LUI
> + * │
> + * │
> + * │ ┌─ P16.MV ──── P16.RI ─── P16.SYSCALL
> + * │ │
> + * │ ├─ P16.SR
> + * │ │
> + * │ ├─ P16.SHIFT
> + * │ │
> + * │ ├─ P16.4x4
> + * │ │
> + * │ ├─ P16C ────── POOL16C_0 ── POOL16C_00
> + * │ │
> + * └─ P16 ─┼─ P16.LB
> + * │
> + * ├─ P16.A1
> + * │
> + * ├─ P16.LH
> + * │
> + * ├─ P16.A2 ──── P.ADDIU[RS5]
> + * │
> + * ├─ P16.ADDU
> + * │
> + * └─ P16.BR ──┬─ P16.JRC
> + * │
> + * └─ P16.BR1
Nice ASCII tree! And you got it fits the 80 chars per line limit =)
> + *
> + *
> + * (FP, DPS, and some minor instruction pools are omitted from the diagram)
> + *
> + */
> +
> NMD::Pool NMD::P_SYSCALL[2] = {
> { instruction , 0 , 0 , 32,
> 0xfffc0000, 0x00080000, &NMD::SYSCALL_32_ , 0,
>
next prev parent reply other threads:[~2019-03-05 12:04 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-04 21:08 [Qemu-devel] [PATCH v7 00/14] Misc target/mips fixes and improvements Aleksandar Markovic
2019-03-04 21:08 ` [Qemu-devel] [PATCH v7 01/14] disas: nanoMIPS: Correct comments to handlers of some DSP instructions Aleksandar Markovic
2019-03-04 21:08 ` [Qemu-devel] [PATCH v7 02/14] disas: nanoMIPS: Add graphical description of pool organization Aleksandar Markovic
2019-03-05 12:04 ` Philippe Mathieu-Daudé [this message]
2019-03-05 12:39 ` Aleksandar Markovic
2019-03-05 14:07 ` Philippe Mathieu-Daudé
2019-03-05 14:08 ` Philippe Mathieu-Daudé
2019-03-05 18:11 ` Aleksandar Markovic
2019-03-04 21:08 ` [Qemu-devel] [PATCH v7 03/14] tests/tcg: target/mips: Add wrappers for various MSA instructions Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 04/14] tests/tcg: target/mips: Add test utilities for 32-bit tests Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 05/14] tests/tcg: target/mips: Add test utilities for 64-bit tests Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 06/14] tests/tcg: target/mips: Fix test utilities for 128-bit tests Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 07/14] tests/tcg: target/mips: Extend functionality of MSA wrapper macros Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 08/14] tests/tcg: target/mips: Add wrappers for some MIPS64R6 instructions Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 09/14] tests/tcg: target/mips: Add tests for MIPS64R6 logic instructions Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 10/14] tests/tcg: target/mips: Add tests for MIPS64R6 bit swap instructions Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 11/14] tests/tcg: target/mips: Add tests for MIPS64R6 bit count instructions Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 12/14] tests/tcg: target/mips: Add tests for MIPS64R6 shift instructions Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 13/14] tests/tcg: target/mips: Add tests for MIPS64R6 int multiply instructions Aleksandar Markovic
2019-03-04 21:09 ` [Qemu-devel] [PATCH v7 14/14] tests/tcg: target/mips: Add tests for MSA pack instructions Aleksandar Markovic
2019-03-05 11:54 ` [Qemu-devel] [PATCH v7 00/14] Misc target/mips fixes and improvements Aleksandar Rikalo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8acd73e1-219f-b5f7-e001-6f6dd086171d@redhat.com \
--to=philmd@redhat.com \
--cc=aleksandar.markovic@rt-rk.com \
--cc=amarkovic@wavecomp.com \
--cc=arikalo@wavecomp.com \
--cc=aurelien@aurel32.net \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).