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Tue, 21 May 2024 16:41:11 +0000 (GMT) Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2848758054; Tue, 21 May 2024 16:41:11 +0000 (GMT) Received: from mamboa4.aus.stglabs.ibm.com (unknown [9.3.84.87]) by smtpav04.wdc07v.mail.ibm.com (Postfix) with ESMTP; Tue, 21 May 2024 16:41:11 +0000 (GMT) Message-ID: <8aebdcbb3feed5b943ca8dc09fae11720447d287.camel@linux.ibm.com> Subject: Re: [PATCH v2 10/12] target/ppc: Implement LDBAR, TTR SPRs From: Miles Glenn To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Daniel Henrique Barboza , Richard Henderson , Chinmay Rath Date: Tue, 21 May 2024 11:41:10 -0500 In-Reply-To: <20240521013029.30082-11-npiggin@gmail.com> References: <20240521013029.30082-1-npiggin@gmail.com> <20240521013029.30082-11-npiggin@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-22.el8) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: WMkLgNJ8b-wbb77Eb6C1ieIfLuVterLo X-Proofpoint-GUID: L-jm1UoorKA7hjUX82JMPBTCw5idcx-e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-21_10,2024-05-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=967 lowpriorityscore=0 priorityscore=1501 suspectscore=0 spamscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405210126 Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles Thanks, Glenn On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote: > LDBAR, TTR are a Power-specific SPRs. These simple implementations > are enough for IBM proprietary firmware for now. > > Signed-off-by: Nicholas Piggin > --- > target/ppc/cpu.h | 2 ++ > target/ppc/cpu_init.c | 10 ++++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 141cbefb4c..823be85d03 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -2098,6 +2098,7 @@ void ppc_compat_add_property(Object *obj, const > char *name, > #define SPR_DEXCR (0x33C) > #define SPR_IC (0x350) > #define SPR_VTB (0x351) > +#define SPR_LDBAR (0x352) > #define SPR_MMCRC (0x353) > #define SPR_PSSCR (0x357) > #define SPR_440_INV0 (0x370) > @@ -2144,6 +2145,7 @@ void ppc_compat_add_property(Object *obj, const > char *name, > #define SPR_440_IVLIM (0x399) > #define SPR_TSCR (0x399) > #define SPR_750_DMAU (0x39A) > +#define SPR_POWER_TTR (0x39A) > #define SPR_750_DMAL (0x39B) > #define SPR_440_RSTCFG (0x39B) > #define SPR_BOOKE_DCDBTRL (0x39C) > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 023b58a3ac..7f2f8e5a4a 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -5784,6 +5784,16 @@ static void > register_power_common_book4_sprs(CPUPPCState *env) > &spr_access_nop, &spr_write_generic, > &spr_access_nop, &spr_write_generic, > 0x00000000); > + spr_register_hv(env, SPR_LDBAR, "LDBAR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_core_lpar_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_POWER_TTR, "TTR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_core_write_generic, > + 0x00000000); > #endif > } >