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Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v5 16/36] tcg: Add tcg_gen_{non}atomic_cmpxchg_i128 Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: alex.bennee@linaro.org References: <20230126043824.54819-1-richard.henderson@linaro.org> <20230126043824.54819-17-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230126043824.54819-17-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.15, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 26/1/23 05:38, Richard Henderson wrote: > This will allow targets to avoid rolling their own. > > Signed-off-by: Richard Henderson > --- > accel/tcg/tcg-runtime.h | 11 +++++ > include/tcg/tcg-op.h | 5 +++ > tcg/tcg-op.c | 85 +++++++++++++++++++++++++++++++++++ > accel/tcg/atomic_common.c.inc | 45 +++++++++++++++++++ > 4 files changed, 146 insertions(+) > +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 cmpv, > + TCGv_i128 newv, TCGArg idx, MemOp memop) > +{ > + if (TCG_TARGET_REG_BITS == 32) { > + /* Inline expansion below is simply too large for 32-bit hosts. */ > + gen_atomic_cx_i128 gen = ((memop & MO_BSWAP) == MO_LE > + ? gen_helper_nonatomic_cmpxchgo_le > + : gen_helper_nonatomic_cmpxchgo_be); > + MemOpIdx oi = make_memop_idx(memop, idx); > + > + tcg_debug_assert((memop & MO_SIZE) == MO_128); > + tcg_debug_assert((memop & MO_SIGN) == 0); > + > + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); > + } else { > + TCGv_i128 oldv = tcg_temp_new_i128(); > + TCGv_i128 tmpv = tcg_temp_new_i128(); > + TCGv_i64 t0 = tcg_temp_new_i64(); > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 z = tcg_constant_i64(0); > + > + tcg_gen_qemu_ld_i128(oldv, addr, idx, memop); > + > + /* Compare i128 */ > + tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); > + tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); > + tcg_gen_or_i64(t0, t0, t1); Can we skip the OR ... > + /* tmpv = equal ? newv : oldv */ > + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, > + TCGV128_LOW(newv), TCGV128_LOW(oldv)); > + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, ... and test t1 here to partially update LO/HI? (we could remove t1 and just use t0 as twice 'xor + movcond' but the code is less readable). > + TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); > + > + /* Unconditional writeback. */ > + tcg_gen_qemu_st_i128(tmpv, addr, idx, memop); > + tcg_gen_mov_i128(retv, oldv); > + > + tcg_temp_free_i64(t0); > + tcg_temp_free_i64(t1); > + tcg_temp_free_i128(tmpv); > + tcg_temp_free_i128(oldv); > + } > +} Reviewed-by: Philippe Mathieu-Daudé