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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
	qemu-devel <qemu-devel@nongnu.org>,
	"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	liweiwei <liweiwei@iscas.ac.cn>,
	Christoph Muellner <christoph.muellner@vrull.eu>
Subject: Re: Host riscv disas is broken
Date: Wed, 16 Oct 2024 20:52:05 -0700	[thread overview]
Message-ID: <8b1e3b44-1cd6-45a2-933c-a7a599598758@linaro.org> (raw)
In-Reply-To: <da7690ea-a02c-4402-b798-fc29bd07451b@linux.alibaba.com>

On 10/16/24 19:57, LIU Zhiwei wrote:
> Hi Richard,
> 
> On 2024/10/17 02:38, Richard Henderson wrote:
>> 2595: if (dec->cfg->ext_zcmop) {
>> 2690:                if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
>> 2716:                        if (!dec->cfg->ext_zcmt) {
>> 2726:                        if (!dec->cfg->ext_zcmp) {
>> 4028:                if (dec->cfg->ext_zimop) {
>> 5044:            if (dec->cfg->ext_zfinx) {
>> 5051:            if (dec->cfg->ext_zfinx) {
>> 5058:            if (dec->cfg->ext_zfinx) {
>> 5065:            if (dec->cfg->ext_zfinx) {
>> 5371:        if (guard_func(cfg)) {
>>
>> This structure comes from RISCVCPU, a target structure.
> Oops. We missed this.
>> There is no such structure for the host, causing null pointer dereferences.
>>
>> The zfinx references can be changed to
>>
>>     dec->cfg && dec->cfg->ext_zfinx
>>
>> but some of them can simply be removed, e.g. zcmop and zimop, which are otherwise 
>> reserved encodings.
> 
> Should we probe the host feature like what we do in tcg backend support and then do the 
> right disassemble according to the probe result?

I don't think there's anything that is currently checked in disas/riscv.c that needs to 
know about the host.  And, as I say above, some of those checks can be eliminated.

Host disassembly needs are limited to what tcg/riscv/ emits.


r~


  reply	other threads:[~2024-10-17  3:53 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-16 18:38 Host riscv disas is broken Richard Henderson
2024-10-17  2:57 ` LIU Zhiwei
2024-10-17  3:52   ` Richard Henderson [this message]
2024-10-17  5:38     ` LIU Zhiwei
2024-12-04  2:45       ` Alistair Francis
2024-12-06  3:39         ` LIU Zhiwei

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