Re: [PATCH for-10.1 10/10] target/arm: Make LD1Q decode and trans fn agree about a->u

[Richard Henderson <richard.henderson@linaro.org>]

On 7/18/25 10:30, Peter Maydell wrote:
> For the LD1Q instruction (gather load of quadwords) we use the
> LD1_zprz pattern with MO_128 elements.  At this element size there is
> no signed vs unsigned distinction, and we only set the 'u' bit in the
> arg_LD1_zprz struct because we share the code and decode struct with
> smaller element sizes.
> 
> However, we set u=0 in the decode pattern line but then accidentally
> asserted that it was 1 in the trans function.  Since our usual convention
> is that the "default" is unsigned and we only mark operations as signed
> when they really do need to extend, change the decode pattern line to
> set u=1 to match the assert.
> 
> Fixes: d2aa9a804ee6 ("target/arm: Implement LD1Q, ST1Q for SVE2p1")
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/arm/tcg/sve.decode | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode
> index a77b725c876..aea7f519730 100644
> --- a/target/arm/tcg/sve.decode
> +++ b/target/arm/tcg/sve.decode
> @@ -1345,7 +1345,7 @@ LD1_zprz        1100010 11 1. ..... 11. ... ..... ..... \
>   
>   # LD1Q
>   LD1_zprz        1100 0100 000 rm:5 101 pg:3 rn:5 rd:5 \
> -                &rprr_gather_load u=0 ff=0 xs=2 esz=4 msz=4 scale=0
> +                &rprr_gather_load u=1 ff=0 xs=2 esz=4 msz=4 scale=0
>   
>   # SVE 64-bit gather load (vector plus immediate)
>   LD1_zpiz        1100010 .. 01 ..... 1.. ... ..... ..... \

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~