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Fri, 18 Jul 2025 14:46:46 -0700 (PDT) Received: from [192.168.101.134] ([75.147.178.105]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b3f2ff62972sm1431258a12.40.2025.07.18.14.46.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Jul 2025 14:46:45 -0700 (PDT) Message-ID: <8b1f32b8-73fb-4cb2-8b86-2f6677cb0286@linaro.org> Date: Fri, 18 Jul 2025 14:46:44 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH for-10.1 10/10] target/arm: Make LD1Q decode and trans fn agree about a->u To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20250718173032.2498900-1-peter.maydell@linaro.org> <20250718173032.2498900-11-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250718173032.2498900-11-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/18/25 10:30, Peter Maydell wrote: > For the LD1Q instruction (gather load of quadwords) we use the > LD1_zprz pattern with MO_128 elements. At this element size there is > no signed vs unsigned distinction, and we only set the 'u' bit in the > arg_LD1_zprz struct because we share the code and decode struct with > smaller element sizes. > > However, we set u=0 in the decode pattern line but then accidentally > asserted that it was 1 in the trans function. Since our usual convention > is that the "default" is unsigned and we only mark operations as signed > when they really do need to extend, change the decode pattern line to > set u=1 to match the assert. > > Fixes: d2aa9a804ee6 ("target/arm: Implement LD1Q, ST1Q for SVE2p1") > Signed-off-by: Peter Maydell > --- > target/arm/tcg/sve.decode | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode > index a77b725c876..aea7f519730 100644 > --- a/target/arm/tcg/sve.decode > +++ b/target/arm/tcg/sve.decode > @@ -1345,7 +1345,7 @@ LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \ > > # LD1Q > LD1_zprz 1100 0100 000 rm:5 101 pg:3 rn:5 rd:5 \ > - &rprr_gather_load u=0 ff=0 xs=2 esz=4 msz=4 scale=0 > + &rprr_gather_load u=1 ff=0 xs=2 esz=4 msz=4 scale=0 > > # SVE 64-bit gather load (vector plus immediate) > LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ Reviewed-by: Richard Henderson r~