Re: [PATCH] target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 only

[Richard Henderson <richard.henderson@linaro.org>]

On 11/21/23 08:46, Peter Maydell wrote:
> The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and
> IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read
> and write the contents of an AArch32-only system register.  The
> architecture requires that they are present only when EL1 can be
> AArch32, but we implement them unconditionally.  This was OK when all
> our CPUs supported AArch32 EL1, but we have quite a lot of CPU models
> now which only support AArch64 at EL1:
>   a64fx
>   cortex-a76
>   cortex-a710
>   neoverse-n1
>   neoverse-n2
>   neoverse-v1
> 
> Only define these registers for CPUs which allow AArch32 EL1.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> I happened to notice this reading through the Arm ARM recently.  This
> is technically a bug, but you'll only notice it if you deliberately
> look at what should be an unimplemented register to see if it UNDEFs,
> so I don't think it's worth either putting in 8.2 or backporting to
> stable.
> ---
>   target/arm/debug_helper.c | 23 +++++++++++++++--------
>   target/arm/helper.c       | 35 +++++++++++++++++++++--------------
>   2 files changed, 36 insertions(+), 22 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~