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[97.126.117.207]) by smtp.gmail.com with ESMTPSA id a3sm22758089pfc.70.2019.07.19.14.31.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jul 2019 14:31:50 -0700 (PDT) To: Peter Maydell References: <20190307170440.3113-1-richard.henderson@linaro.org> <20190307170440.3113-21-richard.henderson@linaro.org> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <8b6a7e87-81d7-503b-80be-6bebdda23b30@linaro.org> Date: Fri, 19 Jul 2019 14:31:48 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: Re: [Qemu-devel] [PATCH v4 20/22] target/arm: Create a TLB entry for tag physical address space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/19/19 8:48 AM, Peter Maydell wrote: > Playing around with this series, I have discovered that if > the board model doesn't create the tag-memory then target/arm/cpu.c > will not create the 'cpu-tag-memory' AddressSpace. But nothing > disables the usage of the target_tlb_bit2, and then when > arm_cpu_tlb_fill() does a tlb_set_page_with_attrs() using > an attrs with target_tlb_bit2 set then we assert in > cpu_asidx_from_attrs() because cpu->num_ases is 2 and > cc->asidx_from_attrs() returned an out of range number (ie 2). Oops. > Is the tag-memory mandatory for MTE? If so we should either > disable MTE if no tag-memory is provided, or else fail > realize of the CPU; not sure which. If it's not mandatory > then we need to avoid asserting :-) I'm not sure. I'll need to study the docs again. There is an MTE support level at which some of the EL0 bits are recognized but no tags are supported: ID_AA64PFR0_EL1.MTE == 1. But that's not quite the same as what you're asking. r~