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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Thu, 11 Jan 2018 07:47:50 -0800
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Subject: Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation
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To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@sifive.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, RISC-V Patches <patches@groups.riscv.org>

On 01/10/2018 06:21 PM, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
> 
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
> 
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
>  target/riscv/instmap.h   |  377 +++++++++
>  target/riscv/translate.c | 1982 ++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 2359 insertions(+)
>  create mode 100644 target/riscv/instmap.h
>  create mode 100644 target/riscv/translate.c

While there is forward progress within translate.c, it would seem that quite a
lot of my v1 comments are not yet addressed.

Also,

> +        if (!riscv_has_ext(env, RVC)) {

You may not access env in this way.  Any code generation differences must be
computable from either unchanging values on the cpu or tb->flags.  MISA is not
unchanging -- you allow runtime modification.

Again, the partial patch I saw from Stefan would fix this.


r~