From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com
Subject: Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR
Date: Tue, 8 Oct 2019 21:37:11 -0400 [thread overview]
Message-ID: <8b816d13-0243-562c-7fa9-96f350935895@linaro.org> (raw)
In-Reply-To: <34350af3b53fadc50bfe4f1fbc452c7d3a8fe8f7.1570572202.git.alistair.francis@wdc.com>
On 10/8/19 6:04 PM, Alistair Francis wrote:
> Instead of relying on atomics to access the MIP register let's update
> our helper function to instead just lock the IO mutex thread before
> writing. This follows the same concept as used in PPC for handling
> interrupts
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 5 ++--
> target/riscv/cpu.h | 9 --------
> target/riscv/cpu_helper.c | 48 +++++++++++++++------------------------
> target/riscv/csr.c | 2 +-
> 4 files changed, 21 insertions(+), 43 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2019-10-09 1:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-08 22:04 [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR Alistair Francis
2019-10-09 1:37 ` Richard Henderson [this message]
2019-10-18 16:51 ` Palmer Dabbelt
2019-10-18 17:44 ` Alistair Francis
2019-10-29 10:49 ` Alistair Francis
2019-10-29 15:14 ` Palmer Dabbelt
2019-10-30 6:54 ` Alistair Francis
2019-11-01 16:58 ` Palmer Dabbelt
2019-10-29 12:03 ` Alex Bennée
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