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[67.216.144.16]) by smtp.gmail.com with ESMTPSA id h65sm220235ywa.62.2019.10.08.18.37.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Oct 2019 18:37:16 -0700 (PDT) Subject: Re: [PATCH v1 1/1] target/riscv: Remove atomic accesses to MIP CSR To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <34350af3b53fadc50bfe4f1fbc452c7d3a8fe8f7.1570572202.git.alistair.francis@wdc.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <8b816d13-0243-562c-7fa9-96f350935895@linaro.org> Date: Tue, 8 Oct 2019 21:37:11 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <34350af3b53fadc50bfe4f1fbc452c7d3a8fe8f7.1570572202.git.alistair.francis@wdc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/8/19 6:04 PM, Alistair Francis wrote: > Instead of relying on atomics to access the MIP register let's update > our helper function to instead just lock the IO mutex thread before > writing. This follows the same concept as used in PPC for handling > interrupts > > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.c | 5 ++-- > target/riscv/cpu.h | 9 -------- > target/riscv/cpu_helper.c | 48 +++++++++++++++------------------------ > target/riscv/csr.c | 2 +- > 4 files changed, 21 insertions(+), 43 deletions(-) Reviewed-by: Richard Henderson r~