From: LIU Zhiwei <baxiantai@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: brad@comstyle.com, Alistair.Francis@wdc.com, palmer@dabbelt.com,
qemu-riscv@nongnu.org
Subject: Re: [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
Date: Wed, 3 Jul 2024 16:46:46 +0800 [thread overview]
Message-ID: <8bba24bf-2a7d-442f-81a5-236d6f119ea5@gmail.com> (raw)
In-Reply-To: <20240627180350.128575-2-richard.henderson@linaro.org>
On 2024/6/28 2:03, Richard Henderson wrote:
> Move detection code out of tcg, similar to other hosts.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> ---
> host/include/riscv/host/cpuinfo.h | 23 +++++++++
> tcg/riscv/tcg-target.h | 46 ++++++++---------
> util/cpuinfo-riscv.c | 85 +++++++++++++++++++++++++++++++
> tcg/riscv/tcg-target.c.inc | 84 +++---------------------------
> util/meson.build | 2 +
> 5 files changed, 139 insertions(+), 101 deletions(-)
> create mode 100644 host/include/riscv/host/cpuinfo.h
> create mode 100644 util/cpuinfo-riscv.c
>
> diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h
> new file mode 100644
> index 0000000000..2b00660e36
> --- /dev/null
> +++ b/host/include/riscv/host/cpuinfo.h
> @@ -0,0 +1,23 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Host specific cpu identification for RISC-V.
> + */
> +
> +#ifndef HOST_CPUINFO_H
> +#define HOST_CPUINFO_H
> +
> +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */
> +#define CPUINFO_ZBA (1u << 1)
> +#define CPUINFO_ZBB (1u << 2)
> +#define CPUINFO_ZICOND (1u << 3)
> +
> +/* Initialized with a constructor. */
> +extern unsigned cpuinfo;
> +
> +/*
> + * We cannot rely on constructor ordering, so other constructors must
> + * use the function interface rather than the variable above.
> + */
> +unsigned cpuinfo_init(void);
> +
> +#endif /* HOST_CPUINFO_H */
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 2c1b680b93..1a347eaf6e 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -25,6 +25,8 @@
> #ifndef RISCV_TCG_TARGET_H
> #define RISCV_TCG_TARGET_H
>
> +#include "host/cpuinfo.h"
> +
> #define TCG_TARGET_INSN_UNIT_SIZE 4
> #define TCG_TARGET_NB_REGS 32
> #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
> @@ -80,18 +82,12 @@ typedef enum {
> #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
> #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
>
> -#if defined(__riscv_arch_test) && defined(__riscv_zbb)
> -# define have_zbb true
> -#else
> -extern bool have_zbb;
> -#endif
> -
> /* optional instructions */
> #define TCG_TARGET_HAS_negsetcond_i32 1
> #define TCG_TARGET_HAS_div_i32 1
> #define TCG_TARGET_HAS_rem_i32 1
> #define TCG_TARGET_HAS_div2_i32 0
> -#define TCG_TARGET_HAS_rot_i32 have_zbb
> +#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_deposit_i32 0
> #define TCG_TARGET_HAS_extract_i32 0
> #define TCG_TARGET_HAS_sextract_i32 0
> @@ -106,17 +102,17 @@ extern bool have_zbb;
> #define TCG_TARGET_HAS_ext16s_i32 1
> #define TCG_TARGET_HAS_ext8u_i32 1
> #define TCG_TARGET_HAS_ext16u_i32 1
> -#define TCG_TARGET_HAS_bswap16_i32 have_zbb
> -#define TCG_TARGET_HAS_bswap32_i32 have_zbb
> +#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_not_i32 1
> -#define TCG_TARGET_HAS_andc_i32 have_zbb
> -#define TCG_TARGET_HAS_orc_i32 have_zbb
> -#define TCG_TARGET_HAS_eqv_i32 have_zbb
> +#define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_nand_i32 0
> #define TCG_TARGET_HAS_nor_i32 0
> -#define TCG_TARGET_HAS_clz_i32 have_zbb
> -#define TCG_TARGET_HAS_ctz_i32 have_zbb
> -#define TCG_TARGET_HAS_ctpop_i32 have_zbb
> +#define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_brcond2 1
> #define TCG_TARGET_HAS_setcond2 1
> #define TCG_TARGET_HAS_qemu_st8_i32 0
> @@ -125,7 +121,7 @@ extern bool have_zbb;
> #define TCG_TARGET_HAS_div_i64 1
> #define TCG_TARGET_HAS_rem_i64 1
> #define TCG_TARGET_HAS_div2_i64 0
> -#define TCG_TARGET_HAS_rot_i64 have_zbb
> +#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_deposit_i64 0
> #define TCG_TARGET_HAS_extract_i64 0
> #define TCG_TARGET_HAS_sextract_i64 0
> @@ -137,18 +133,18 @@ extern bool have_zbb;
> #define TCG_TARGET_HAS_ext8u_i64 1
> #define TCG_TARGET_HAS_ext16u_i64 1
> #define TCG_TARGET_HAS_ext32u_i64 1
> -#define TCG_TARGET_HAS_bswap16_i64 have_zbb
> -#define TCG_TARGET_HAS_bswap32_i64 have_zbb
> -#define TCG_TARGET_HAS_bswap64_i64 have_zbb
> +#define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_not_i64 1
> -#define TCG_TARGET_HAS_andc_i64 have_zbb
> -#define TCG_TARGET_HAS_orc_i64 have_zbb
> -#define TCG_TARGET_HAS_eqv_i64 have_zbb
> +#define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_nand_i64 0
> #define TCG_TARGET_HAS_nor_i64 0
> -#define TCG_TARGET_HAS_clz_i64 have_zbb
> -#define TCG_TARGET_HAS_ctz_i64 have_zbb
> -#define TCG_TARGET_HAS_ctpop_i64 have_zbb
> +#define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB)
> +#define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB)
> #define TCG_TARGET_HAS_add2_i64 1
> #define TCG_TARGET_HAS_sub2_i64 1
> #define TCG_TARGET_HAS_mulu2_i64 0
> diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c
> new file mode 100644
> index 0000000000..6b97100620
> --- /dev/null
> +++ b/util/cpuinfo-riscv.c
> @@ -0,0 +1,85 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Host specific cpu identification for RISC-V.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "host/cpuinfo.h"
> +
> +unsigned cpuinfo;
> +static volatile sig_atomic_t got_sigill;
> +
> +static void sigill_handler(int signo, siginfo_t *si, void *data)
> +{
> + /* Skip the faulty instruction */
> + ucontext_t *uc = (ucontext_t *)data;
> + uc->uc_mcontext.__gregs[REG_PC] += 4;
> +
> + got_sigill = 1;
> +}
> +
> +/* Called both as constructor and (possibly) via other constructors. */
> +unsigned __attribute__((constructor)) cpuinfo_init(void)
> +{
> + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND;
> + unsigned info = cpuinfo;
> +
> + if (info) {
> + return info;
> + }
> +
> + /* Test for compile-time settings. */
> +#if defined(__riscv_arch_test) && defined(__riscv_zba)
> + info |= CPUINFO_ZBA;
> +#endif
> +#if defined(__riscv_arch_test) && defined(__riscv_zbb)
> + info |= CPUINFO_ZBB;
> +#endif
> +#if defined(__riscv_arch_test) && defined(__riscv_zicond)
> + info |= CPUINFO_ZICOND;
> +#endif
> + left &= ~info;
> +
> + if (left) {
> + struct sigaction sa_old, sa_new;
> +
> + memset(&sa_new, 0, sizeof(sa_new));
> + sa_new.sa_flags = SA_SIGINFO;
> + sa_new.sa_sigaction = sigill_handler;
> + sigaction(SIGILL, &sa_new, &sa_old);
> +
> + if (left & CPUINFO_ZBA) {
> + /* Probe for Zba: add.uw zero,zero,zero. */
> + got_sigill = 0;
> + asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero"
> + : : : "memory");
> + info |= !got_sigill * CPUINFO_ZBA;
> + left &= ~CPUINFO_ZBA;
> + }
> +
> + if (left & CPUINFO_ZBB) {
> + /* Probe for Zba: andn zero,zero,zero. */
> + got_sigill = 0;
> + asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero"
> + : : : "memory");
> + info |= !got_sigill * CPUINFO_ZBB;
> + left &= ~CPUINFO_ZBB;
> + }
> +
> + if (left & CPUINFO_ZICOND) {
> + /* Probe for Zicond: czero.eqz zero,zero,zero. */
> + got_sigill = 0;
> + asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero"
> + : : : "memory");
> + info |= !got_sigill * CPUINFO_ZICOND;
> + left &= ~CPUINFO_ZICOND;
> + }
> +
> + sigaction(SIGILL, &sa_old, NULL);
> + assert(left == 0);
> + }
> +
> + info |= CPUINFO_ALWAYS;
> + cpuinfo = info;
> + return info;
> +}
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 639363039b..d334857226 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -113,20 +113,6 @@ static const int tcg_target_call_iarg_regs[] = {
> TCG_REG_A7,
> };
>
> -#ifndef have_zbb
> -bool have_zbb;
> -#endif
> -#if defined(__riscv_arch_test) && defined(__riscv_zba)
> -# define have_zba true
> -#else
> -static bool have_zba;
> -#endif
> -#if defined(__riscv_arch_test) && defined(__riscv_zicond)
> -# define have_zicond true
> -#else
> -static bool have_zicond;
> -#endif
> -
> static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> {
> tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> @@ -594,7 +580,7 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
>
> static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
> {
> - if (have_zbb) {
> + if (cpuinfo & CPUINFO_ZBB) {
> tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO);
> } else {
> tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> @@ -604,7 +590,7 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
>
> static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
> {
> - if (have_zba) {
> + if (cpuinfo & CPUINFO_ZBA) {
> tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO);
> } else {
> tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
> @@ -614,7 +600,7 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
>
> static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> {
> - if (have_zbb) {
> + if (cpuinfo & CPUINFO_ZBB) {
> tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0);
> } else {
> tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
> @@ -624,7 +610,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
>
> static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
> {
> - if (have_zbb) {
> + if (cpuinfo & CPUINFO_ZBB) {
> tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0);
> } else {
> tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
> @@ -1080,7 +1066,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
> int tmpflags;
> TCGReg t;
>
> - if (!have_zicond && (!c_cmp2 || cmp2 == 0)) {
> + if (!(cpuinfo & CPUINFO_ZICOND) && (!c_cmp2 || cmp2 == 0)) {
> tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2,
> val1, c_val1, val2, c_val2);
> return;
> @@ -1089,7 +1075,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
> tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, cmp1, cmp2, c_cmp2);
> t = tmpflags & ~SETCOND_FLAGS;
>
> - if (have_zicond) {
> + if (cpuinfo & CPUINFO_ZICOND) {
> if (tmpflags & SETCOND_INV) {
> tcg_out_movcond_zicond(s, ret, t, val2, c_val2, val1, c_val1);
> } else {
> @@ -1304,7 +1290,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
> /* TLB Hit - translate address using addend. */
> if (addr_type != TCG_TYPE_I32) {
> tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
> - } else if (have_zba) {
> + } else if (cpuinfo & CPUINFO_ZBA) {
> tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0,
> addr_reg, TCG_REG_TMP2);
> } else {
> @@ -1335,7 +1321,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase,
> if (addr_type != TCG_TYPE_I32) {
> tcg_out_opc_reg(s, OPC_ADD, base, addr_reg,
> TCG_GUEST_BASE_REG);
> - } else if (have_zba) {
> + } else if (cpuinfo & CPUINFO_ZBA) {
> tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg,
> TCG_GUEST_BASE_REG);
> } else {
> @@ -2110,62 +2096,8 @@ static void tcg_out_tb_start(TCGContext *s)
> /* nothing to do */
> }
>
> -static volatile sig_atomic_t got_sigill;
> -
> -static void sigill_handler(int signo, siginfo_t *si, void *data)
> -{
> - /* Skip the faulty instruction */
> - ucontext_t *uc = (ucontext_t *)data;
> - uc->uc_mcontext.__gregs[REG_PC] += 4;
> -
> - got_sigill = 1;
> -}
> -
> -static void tcg_target_detect_isa(void)
> -{
> -#if !defined(have_zba) || !defined(have_zbb) || !defined(have_zicond)
> - /*
> - * TODO: It is expected that this will be determinable via
> - * linux riscv_hwprobe syscall, not yet merged.
> - * In the meantime, test via sigill.
> - */
> -
> - struct sigaction sa_old, sa_new;
> -
> - memset(&sa_new, 0, sizeof(sa_new));
> - sa_new.sa_flags = SA_SIGINFO;
> - sa_new.sa_sigaction = sigill_handler;
> - sigaction(SIGILL, &sa_new, &sa_old);
> -
> -#ifndef have_zba
> - /* Probe for Zba: add.uw zero,zero,zero. */
> - got_sigill = 0;
> - asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" : : : "memory");
> - have_zba = !got_sigill;
> -#endif
> -
> -#ifndef have_zbb
> - /* Probe for Zba: andn zero,zero,zero. */
> - got_sigill = 0;
> - asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" : : : "memory");
> - have_zbb = !got_sigill;
> -#endif
> -
> -#ifndef have_zicond
> - /* Probe for Zicond: czero.eqz zero,zero,zero. */
> - got_sigill = 0;
> - asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" : : : "memory");
> - have_zicond = !got_sigill;
> -#endif
> -
> - sigaction(SIGILL, &sa_old, NULL);
> -#endif
> -}
> -
> static void tcg_target_init(TCGContext *s)
> {
> - tcg_target_detect_isa();
> -
> tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
> tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
>
> diff --git a/util/meson.build b/util/meson.build
> index 72b505df11..5d8bef9891 100644
> --- a/util/meson.build
> +++ b/util/meson.build
> @@ -127,4 +127,6 @@ elif cpu == 'loongarch64'
> util_ss.add(files('cpuinfo-loongarch.c'))
> elif cpu in ['ppc', 'ppc64']
> util_ss.add(files('cpuinfo-ppc.c'))
> +elif cpu in ['riscv32', 'riscv64']
> + util_ss.add(files('cpuinfo-riscv.c'))
> endif
next prev parent reply other threads:[~2024-07-03 8:48 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-27 18:03 [PATCH 0/3] util: Add cpuinfo support for riscv Richard Henderson
2024-06-27 18:03 ` [PATCH 1/3] util/cpuinfo-riscv: Support host/cpuinfo.h " Richard Henderson
2024-07-02 19:55 ` Philippe Mathieu-Daudé
2024-07-02 23:04 ` Richard Henderson
2024-07-03 7:32 ` Philippe Mathieu-Daudé
2024-07-02 22:17 ` Daniel Henrique Barboza
2024-07-02 23:56 ` Alistair Francis
2024-07-03 8:46 ` LIU Zhiwei [this message]
2024-06-27 18:03 ` [PATCH 2/3] util/cpuinfo-riscv: Support OpenBSD signal frame Richard Henderson
2024-07-02 19:58 ` Philippe Mathieu-Daudé
2024-07-02 22:16 ` Daniel Henrique Barboza
2024-07-02 23:56 ` Alistair Francis
2024-06-27 18:03 ` [PATCH 3/3] util/cpuinfo-riscv: Use linux __riscv_hwprobe syscall Richard Henderson
2024-07-02 22:15 ` Daniel Henrique Barboza
2024-07-02 23:08 ` Richard Henderson
2024-07-02 23:58 ` Alistair Francis
2024-07-02 16:26 ` [PATCH 0/3] util: Add cpuinfo support for riscv Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8bba24bf-2a7d-442f-81a5-236d6f119ea5@gmail.com \
--to=baxiantai@gmail.com \
--cc=Alistair.Francis@wdc.com \
--cc=brad@comstyle.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).