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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71df0d4665dsm8273594b3a.116.2024.10.09.16.05.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Oct 2024 16:05:15 -0700 (PDT) Message-ID: <8bbac2bf-704a-4c4c-ae7a-996f5a04038f@linaro.org> Date: Wed, 9 Oct 2024 16:05:14 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/23] accel/tcg: Split out tlbfast_flush_range_locked Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20241009150855.804605-1-richard.henderson@linaro.org> <20241009150855.804605-5-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20241009150855.804605-5-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/9/24 08:08, Richard Henderson wrote: > While this may at present be overly complicated for use > by single page flushes, do so with the expectation that > this will eventually allow simplification of large pages. > > Signed-off-by: Richard Henderson > --- > accel/tcg/cputlb.c | 61 +++++++++++++++++++++++++--------------------- > 1 file changed, 33 insertions(+), 28 deletions(-) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index e37af24525..6773874f2d 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -520,10 +520,37 @@ static inline void tlb_flush_vtlb_page_locked(CPUState *cpu, int mmu_idx, > tlb_flush_vtlb_page_mask_locked(cpu, mmu_idx, page, -1); > } > > +static void tlbfast_flush_range_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast, > + vaddr addr, vaddr len, vaddr mask) > +{ > + /* > + * If @mask is smaller than the tlb size, there may be multiple entries > + * within the TLB; for now, just flush the entire TLB. > + * Otherwise all addresses that match under @mask hit the same TLB entry. > + * > + * If @len is larger than the tlb size, then it will take longer to > + * test all of the entries in the TLB than it will to flush it all. > + */ > + if (mask < fast->mask || len > fast->mask) { > + tlbfast_flush_locked(desc, fast); > + return; > + } > + > + for (vaddr i = 0; i < len; i += TARGET_PAGE_SIZE) { > + vaddr page = addr + i; > + CPUTLBEntry *entry = tlbfast_entry(fast, page); > + > + if (tlb_flush_entry_mask_locked(entry, page, mask)) { > + desc->n_used_entries--; > + } > + } > +} > + > static void tlb_flush_page_locked(CPUState *cpu, int midx, vaddr page) > { > - vaddr lp_addr = cpu->neg.tlb.d[midx].large_page_addr; > - vaddr lp_mask = cpu->neg.tlb.d[midx].large_page_mask; > + CPUTLBDesc *desc = &cpu->neg.tlb.d[midx]; > + vaddr lp_addr = desc->large_page_addr; > + vaddr lp_mask = desc->large_page_mask; > > /* Check if we need to flush due to large pages. */ > if ((page & lp_mask) == lp_addr) { > @@ -532,9 +559,8 @@ static void tlb_flush_page_locked(CPUState *cpu, int midx, vaddr page) > midx, lp_addr, lp_mask); > tlb_flush_one_mmuidx_locked(cpu, midx, get_clock_realtime()); > } else { > - if (tlb_flush_entry_locked(tlb_entry(cpu, midx, page), page)) { > - tlb_n_used_entries_dec(cpu, midx); > - } > + tlbfast_flush_range_locked(desc, &cpu->neg.tlb.f[midx], > + page, TARGET_PAGE_SIZE, -1); > tlb_flush_vtlb_page_locked(cpu, midx, page); > } > } > @@ -689,24 +715,6 @@ static void tlb_flush_range_locked(CPUState *cpu, int midx, > CPUTLBDescFast *f = &cpu->neg.tlb.f[midx]; > vaddr mask = MAKE_64BIT_MASK(0, bits); > > - /* > - * If @bits is smaller than the tlb size, there may be multiple entries > - * within the TLB; otherwise all addresses that match under @mask hit > - * the same TLB entry. > - * TODO: Perhaps allow bits to be a few bits less than the size. > - * For now, just flush the entire TLB. > - * > - * If @len is larger than the tlb size, then it will take longer to > - * test all of the entries in the TLB than it will to flush it all. > - */ > - if (mask < f->mask || len > f->mask) { > - tlb_debug("forcing full flush midx %d (" > - "%016" VADDR_PRIx "/%016" VADDR_PRIx "+%016" VADDR_PRIx ")\n", > - midx, addr, mask, len); > - tlb_flush_one_mmuidx_locked(cpu, midx, get_clock_realtime()); > - return; > - } > - > /* > * Check if we need to flush due to large pages. > * Because large_page_mask contains all 1's from the msb, > @@ -720,13 +728,10 @@ static void tlb_flush_range_locked(CPUState *cpu, int midx, > return; > } > > + tlbfast_flush_range_locked(d, f, addr, len, mask); > + > for (vaddr i = 0; i < len; i += TARGET_PAGE_SIZE) { > vaddr page = addr + i; > - CPUTLBEntry *entry = tlb_entry(cpu, midx, page); > - > - if (tlb_flush_entry_mask_locked(entry, page, mask)) { > - tlb_n_used_entries_dec(cpu, midx); > - } > tlb_flush_vtlb_page_mask_locked(cpu, midx, page, mask); > } > } Why don't we have the same kind of change for tlb_flush_vtlb_page_mask_locked? We know have two loops (for entry mask, and for page mask).