From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,
"cfu@mips.com" <cfu@mips.com>,
"arikalo@gmail.com" <arikalo@gmail.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>
Subject: Re: [PATCH v2 1/8] Add CP0 MemoryMapID register implementation
Date: Sat, 26 Oct 2024 01:58:26 -0300 [thread overview]
Message-ID: <8bc8a3cb-6083-4b8d-af6a-2fcde3666ffe@linaro.org> (raw)
In-Reply-To: <AM9PR09MB4851FB6034EDB7FA191BA47E84402@AM9PR09MB4851.eurprd09.prod.outlook.com>
On 18/10/24 10:18, Aleksandar Rakic wrote:
> Add CP0 MemoryMapID register implementation.
>
> Cherry-picked 9e0cb40adb110c2c76e2e97719ba8afcce72bcf5
> from https://github.com/MIPS/gnutools-qemu
>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> ---
> target/mips/sysemu/machine.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
Queued rewording commit description as:
target/mips: Migrate TLB MemoryMapID register
Include CP0 MemoryMapID register in migration state.
Fixes: 99029be1c28 ("target/mips: Add implementation
of GINVT instruction")
Thanks,
Phil.
prev parent reply other threads:[~2024-10-26 4:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-18 13:18 [PATCH v2 1/8] Add CP0 MemoryMapID register implementation Aleksandar Rakic
2024-10-19 7:43 ` Aleksandar Rikalo
2024-10-26 4:58 ` Philippe Mathieu-Daudé [this message]
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