[PATCH v2 1/8] Add CP0 MemoryMapID register implementation

[PATCH v2 1/8] Add CP0 MemoryMapID register implementation

[Aleksandar Rakic]

Add CP0 MemoryMapID register implementation.

Cherry-picked 9e0cb40adb110c2c76e2e97719ba8afcce72bcf5
from https://github.com/MIPS/gnutools-qemu

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
---
 target/mips/sysemu/machine.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c
index 213fd637fc..91cd9f1900 100644
--- a/target/mips/sysemu/machine.c
+++ b/target/mips/sysemu/machine.c
@@ -142,6 +142,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size,
     qemu_get_betls(f, &v->VPN);
     qemu_get_be32s(f, &v->PageMask);
     qemu_get_be16s(f, &v->ASID);
+    qemu_get_be32s(f, &v->MMID);
     qemu_get_be16s(f, &flags);
     v->G = (flags >> 10) & 1;
     v->C0 = (flags >> 7) & 3;
@@ -167,6 +168,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size,
     r4k_tlb_t *v = pv;
 
     uint16_t asid = v->ASID;
+    uint32_t mmid = v->MMID;
     uint16_t flags = ((v->EHINV << 15) |
                       (v->RI1 << 14) |
                       (v->RI0 << 13) |
@@ -183,6 +185,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size,
     qemu_put_betls(f, &v->VPN);
     qemu_put_be32s(f, &v->PageMask);
     qemu_put_be16s(f, &asid);
+    qemu_put_be32s(f, &mmid);
     qemu_put_be16s(f, &flags);
     qemu_put_be64s(f, &v->PFN[0]);
     qemu_put_be64s(f, &v->PFN[1]);
@@ -204,8 +207,8 @@ static const VMStateInfo vmstate_info_tlb = {
 
 static const VMStateDescription vmstate_tlb = {
     .name = "cpu/tlb",
-    .version_id = 2,
-    .minimum_version_id = 2,
+    .version_id = 3,
+    .minimum_version_id = 3,
     .fields = (const VMStateField[]) {
         VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
         VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
-- 
2.34.1

Re: [PATCH v2 1/8] Add CP0 MemoryMapID register implementation

[Aleksandar Rikalo]

[-- Attachment #1: Type: text/plain, Size: 501 bytes --]

Add CP0 MemoryMapID register implementation.
>
> Cherry-picked 9e0cb40adb110c2c76e2e97719ba8afcce72bcf5
> from https://github.com/MIPS/gnutools-qemu
>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> ---
>  target/mips/sysemu/machine.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)


Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>

-- Aleksandar

[-- Attachment #2: Type: text/html, Size: 1158 bytes --]

Re: [PATCH v2 1/8] Add CP0 MemoryMapID register implementation

[Philippe Mathieu-Daudé]

On 18/10/24 10:18, Aleksandar Rakic wrote:
> Add CP0 MemoryMapID register implementation.
> 
> Cherry-picked 9e0cb40adb110c2c76e2e97719ba8afcce72bcf5
> from https://github.com/MIPS/gnutools-qemu
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
> ---
>   target/mips/sysemu/machine.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)

Queued rewording commit description as:

     target/mips: Migrate TLB MemoryMapID register

     Include CP0 MemoryMapID register in migration state.

     Fixes: 99029be1c28 ("target/mips: Add implementation
     of GINVT instruction")

Thanks,

Phil.