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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-459dc7e1ddesm223988975e9.27.2025.08.08.09.26.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Aug 2025 09:26:45 -0700 (PDT) Message-ID: <8be60d9d-ee2d-439c-8d55-c0349939d27a@linaro.org> Date: Fri, 8 Aug 2025 18:26:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 10/14] hw/riscv: Add support for RISCV CPS To: Djordje Todorovic , "qemu-devel@nongnu.org" Cc: "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" References: <20250717093833.402237-1-djordje.todorovic@htecgroup.com> <20250717093833.402237-11-djordje.todorovic@htecgroup.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250717093833.402237-11-djordje.todorovic@htecgroup.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 17/7/25 11:38, Djordje Todorovic wrote: > Add support for the Coherent Processing System for RISC-V. > This enables SMP support for RISC-V boards that require > cache-coherent multiprocessor systems. > > Signed-off-by: Chao-ying Fu > Signed-off-by: Djordje Todorovic > --- > hw/misc/Kconfig | 5 ++ > hw/riscv/cps.c | 197 +++++++++++++++++++++++++++++++++++++++++ > hw/riscv/meson.build | 2 + > include/hw/riscv/cps.h | 76 ++++++++++++++++ > 4 files changed, 280 insertions(+) > create mode 100644 hw/riscv/cps.c > create mode 100644 include/hw/riscv/cps.h > +static void main_cpu_reset(void *opaque) > +{ > + RISCVCPU *cpu = opaque; > + CPUState *cs = CPU(cpu); If you call in [*]: qemu_register_reset(main_cpu_reset, s->cpus[i]); then here you can just do: CPUState *cs = opaque; > + > + cpu_reset(cs); > +} > + > +static void riscv_cps_realize(DeviceState *dev, Error **errp) > +{ > + RISCVCPSState *s = RISCV_CPS(dev); > + RISCVCPU *cpu; > + int i; > + Please check num_vp range. > + /* Allocate CPU array */ > + s->cpus = g_new0(CPUState *, s->num_vp); > + > + /* Set up cpu_index and mhartid for avaiable CPUs. */ > + int harts_in_cluster = s->num_hart * s->num_core; > + int num_of_clusters = s->num_vp / harts_in_cluster; > + for (i = 0; i < s->num_vp; i++) { > + cpu = RISCV_CPU(object_new(s->cpu_type)); > + > + /* All VPs are halted on reset. Leave powering up to CPC. */ > + object_property_set_bool(OBJECT(cpu), "start-powered-off", true, > + &error_abort); > + > + if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) { > + return; > + } > + > + /* Store CPU in array */ > + s->cpus[i] = CPU(cpu); > + > + /* Set up mhartid */ > + int cluster_id = i / harts_in_cluster; > + int hart_id = (i % harts_in_cluster) % s->num_hart; > + int core_id = (i % harts_in_cluster) / s->num_hart; > + int mhartid = (cluster_id << MHARTID_CLUSTER_SHIFT) + > + (core_id << MHARTID_CORE_SHIFT) + > + (hart_id << MHARTID_HART_SHIFT); > + cpu->env.mhartid = mhartid; > + qemu_register_reset(main_cpu_reset, cpu); [*] > + } > + > + /* Cluster Power Controller */ > + object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_RISCV_CPC); > + object_property_set_uint(OBJECT(&s->cpc), "cluster-id", 0, > + &error_abort); > + object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp, > + &error_abort); > + object_property_set_uint(OBJECT(&s->cpc), "num-hart", s->num_hart, > + &error_abort); > + object_property_set_uint(OBJECT(&s->cpc), "num-core", s->num_core, > + &error_abort); > + object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1, > + &error_abort); (1 is already the default) > + > + /* Pass CPU array to CPC */ > + s->cpc.cpus = s->cpus; Please do that using a link property. > + > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) { > + return; > + } > + > + memory_region_add_subregion(&s->container, 0, > + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); > + > + /* Global Configuration Registers */ > + object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_RISCV_GCR); > + object_property_set_uint(OBJECT(&s->gcr), "cluster-id", 0, > + &error_abort); > + object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, > + &error_abort); > + object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0xa00, > + &error_abort); > + object_property_set_int(OBJECT(&s->gcr), "gcr-base", s->gcr_base, > + &error_abort); > + object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), > + &error_abort); > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { > + return; > + } > + > + memory_region_add_subregion(&s->container, s->gcr_base, > + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); > + > + for (i = 0; i < num_of_clusters; i++) { > + uint64_t cm_base = GLOBAL_CM_BASE + (CM_SIZE * i); > + uint32_t hartid_base = i << MHARTID_CLUSTER_SHIFT; > + s->aplic = riscv_aplic_create(cm_base + AIA_PLIC_M_OFFSET, > + AIA_PLIC_M_SIZE, > + hartid_base, /* hartid_base */ > + MAX_HARTS, /* num_harts */ > + APLIC_NUM_SOURCES, > + APLIC_NUM_PRIO_BITS, > + false, true, NULL); > + riscv_aplic_create(cm_base + AIA_PLIC_S_OFFSET, > + AIA_PLIC_S_SIZE, > + hartid_base, /* hartid_base */ > + MAX_HARTS, /* num_harts */ > + APLIC_NUM_SOURCES, > + APLIC_NUM_PRIO_BITS, > + false, false, s->aplic); > + /* PLIC changes msi_nonbroken to ture. We revert the change. */ > + msi_nonbroken = false; > + riscv_aclint_swi_create(cm_base + AIA_CLINT_OFFSET, > + hartid_base, MAX_HARTS, false); > + riscv_aclint_mtimer_create(cm_base + AIA_CLINT_OFFSET + > + RISCV_ACLINT_SWI_SIZE, > + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, > + hartid_base, > + MAX_HARTS, > + RISCV_ACLINT_DEFAULT_MTIMECMP, > + RISCV_ACLINT_DEFAULT_MTIME, > + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); > + } > +}