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[95.126.194.9]) by smtp.gmail.com with ESMTPSA id r17sm18022231wmq.5.2021.11.20.00.06.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 20 Nov 2021 00:06:01 -0800 (PST) Subject: Re: [PATCH v11 06/26] target/loongarch: Add fixed point bit instruction translation To: Song Gao , qemu-devel@nongnu.org References: <1637302410-24632-1-git-send-email-gaosong@loongson.cn> <1637302410-24632-7-git-send-email-gaosong@loongson.cn> From: Richard Henderson Message-ID: <8c4b8bff-9502-0a2c-3ecd-3b1156a69e81@linaro.org> Date: Sat, 20 Nov 2021 09:05:58 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <1637302410-24632-7-git-send-email-gaosong@loongson.cn> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::42c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -38 X-Spam_score: -3.9 X-Spam_bar: --- X-Spam_report: (-3.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.625, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiaojuan Yang , laurent@vivier.eu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/19/21 7:13 AM, Song Gao wrote: > +static bool gen_rr(DisasContext *ctx, arg_rr *a, > + DisasExtend src_ext, DisasExtend dst_ext, > + void (*func)(TCGv, TCGv)) > +{ > + TCGv dest = gpr_dst(ctx, a->rd, dst_ext); > + TCGv src1 = gpr_src(ctx, a->rj, src_ext); > + > + func(dest, src1); > + > + if (dst_ext) { > + gen_set_gpr(a->rd, dest, dst_ext); > + } Again, I think you should call gen_set_gpr unconditionally. > +static bool trans_bytepick_w(DisasContext *ctx, arg_bytepick_w *a) > +{ > + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); > + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); > + TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); > + > + tcg_gen_concat_tl_i64(dest, src1, src2); > + tcg_gen_sextract_i64(dest, dest, (32 - (a->sa) * 8), 32); > + > + return true; > +} Better to use gen_rrr_sa. > +static bool trans_bytepick_d(DisasContext *ctx, arg_bytepick_d *a) > +{ > + TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); > + TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); > + TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); > + > + tcg_gen_extract2_i64(dest, src1, src2, (64 - (a->sa) * 8)); > + return true; > +} Likewise. > +static void gen_ctz_w(TCGv dest, TCGv src1) > +{ > + tcg_gen_ori_tl(dest, src1, (target_ulong)MAKE_64BIT_MASK(32, 32)); > + tcg_gen_ctzi_tl(dest, dest, 32); This should be TARGET_LONG_BITS. It will never happen, because the value is not zero per the OR, but it's what is most efficient for a tcg backend that naturally produces TARGET_LONG_BITS for a TL-sized ctz. > +} > + > +static void gen_cto_w(TCGv dest, TCGv src1) > +{ > + tcg_gen_not_tl(dest, src1); > + tcg_gen_ext32u_tl(dest, dest); > + gen_ctz_w(dest, dest); > +} The EXT32U here is useless, as the OR within gen_ctz_w overrides it. > +&rr_2bw rd rj msbw lsbw > +&rr_2bd rd rj msbd lsbd Merge these. r~