Re: [PATCH 1/3] intel_iommu: Send IQE event when setting reserved bit in IQT_TAIL

[Yi Liu <yi.l.liu@intel.com>]

On 2024/11/4 20:55, Zhenzhong Duan wrote:
> According to VTD spec, Figure 11-22, Invalidation Queue Tail Register,
> "When Descriptor Width (DW) field in Invalidation Queue Address Register
> (IQA_REG) is Set (256-bit descriptors), hardware treats bit-4 as reserved
> and a value of 1 in the bit will result in invalidation queue error."
> 
> Current code missed to send IQE event to guest, fix it.

a nit: mention the spec revision as well since the Figure number may be
modified.

Reviewed-by: Yi Liu <yi.l.liu@intel.com>

> 
> Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support")
> Suggested-by: Yi Liu <yi.l.liu@intel.com>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
>   hw/i386/intel_iommu.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 8612d0917b..1ecfe47963 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2847,6 +2847,7 @@ static void vtd_handle_iqt_write(IntelIOMMUState *s)
>       if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) {
>           error_report_once("%s: RSV bit is set: val=0x%"PRIx64,
>                             __func__, val);
> +        vtd_handle_inv_queue_error(s);
>           return;
>       }
>       s->iq_tail = VTD_IQT_QT(s->iq_dw, val);

-- 
Regards,
Yi Liu