From: Richard Henderson <richard.henderson@linaro.org>
To: Michael Clark <mjc@sifive.com>, qemu-devel@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
"Emilio G . Cota" <cota@braap.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
patches@groups.riscv.org
Subject: Re: [Qemu-devel] [PATCH v1] RISC-V: Add misa to DisasContext
Date: Wed, 9 May 2018 08:12:21 -0700 [thread overview]
Message-ID: <8c7eb58c-f51d-30e9-f5ba-02b365797fd3@linaro.org> (raw)
In-Reply-To: <1525858768-325-1-git-send-email-mjc@sifive.com>
On 05/09/2018 02:39 AM, Michael Clark wrote:
> gen methods should access state from DisasContext. Add misa
> field to the DisasContext struct and remove CPURISCVState
> argument from all gen methods.
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Cc: Emilio G. Cota <cota@braap.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
> target/riscv/translate.c | 74 ++++++++++++++++++++++++++----------------------
> 1 file changed, 40 insertions(+), 34 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2018-05-09 15:12 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-09 9:39 [Qemu-devel] [PATCH v1] RISC-V: Add misa to DisasContext Michael Clark
2018-05-09 15:12 ` Richard Henderson [this message]
2018-05-10 1:37 ` Philippe Mathieu-Daudé
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